Non-volatile Memory Pipeline Circuit Repair
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Solution Overview
Problem
Non-volatile memory devices face challenges in achieving fast operation speeds, which are necessary as system operation frequencies increase, due to their inherently slower read and write speeds compared to volatile memory devices.
Innovation Solution
The implementation of a non-volatile memory device with a memory cell array that includes both normal and redundancy memory cells, coupled with a pipeline circuit that operates in a pipeline manner, selectively using redundancy data to repair and transmit data during consecutive clock cycles, enhancing operational speed through a combination of row and column decoders, page buffers, and repair circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If non-volatile memory device uses traditional architecture without pipeline circuit, then data can be transmitted, but operation speed is slow
Solution Approach 1:
The memory device is segmented into normal memory cells and redundancy memory cells arranged in separate columns. The column decoder is divided into normal column decoder and redundancy column decoder that operate independently. This segmentation allows parallel processing of normal and redundant data paths, improving operation speed without significantly increasing overall device complexity.
Solution Approach 2:
The pipeline circuit performs preliminary actions by pre-charging bit lines and pre-positioning data in page buffers before the actual read operation completes. The repair circuit is prepared in advance to replace defective data with redundant data. These preliminary actions reduce the critical path delay and improve operation speed.
2Speed
If non-volatile memory device increases operation frequency to match system requirements, then system compatibility improves, but data transmission accuracy deteriorates due to slower inherent speed
Solution Approach 1:
The patent implements beforehand cushioning by providing redundancy memory cells and redundancy bit lines that serve as backup pathways. When normal data transmission fails or is defective, the repair control circuit activates the redundancy path in advance, ensuring data accuracy is maintained even at higher operation frequencies where errors are more likely to occur.
Solution Approach 2:
The repair control circuit acts as an intermediary between the normal memory path and redundancy memory path. It monitors data integrity and mediates the switching between normal and redundant data sources, ensuring accurate data transmission is maintained regardless of operation frequency increases.
3Productivity
If non-volatile memory device uses redundancy memory cells and pipeline circuit, then operation speed increases, but device complexity increases
Solution Approach 1:
The redundancy memory cells serve multiple functions: they act as backup storage for defective data, provide additional data bits for error correction, and can be activated selectively based on defect locations. The pipeline circuit also serves dual purposes by handling both normal data transmission and repair operations. This multi-functionality increases productivity while minimizing the additional complexity introduced by redundancy components.
Data Source
AI summary
A non-volatile memory device may include a memory cell array, a page buffer, a column decoder, a column selection circuit and a repair circuit. The memory cell array includes normal memory cells and redundancy memory cells. In one example, the page buffer may load normal data and redundancy data from the memory cell array. The column decoder may generate a normal column selection signal and a redundancy column selection signal in response to a column address. The column selection circuit may select the normal data and redundancy data in response to the normal column selection signal and redundancy column selection signal. The repair circuit may then output one of the normal data and redundancy data.