NVDIMM Cache for Deterministic Memory Access Latency
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Solution Overview
Problem
Conventional dual in-line memory modules (DIMMs) face issues with data persistence and deterministic memory access latency, as they rely on volatile DRAM, leading to unpredictable behavior and data loss during power interruptions, and nondeterministic response times due to the use of nonvolatile random access memory (NVRAM) with varying access latencies.
Innovation Solution
A nonvolatile dual in-line memory module (NVDIMM) is introduced, incorporating a cache with lower latency memory (such as DRAM) to manage memory access requests deterministically and persistently store data using nonvolatile random access memory (NVRAM), employing a command-response protocol and error correction mechanisms to reorder out-of-order data and handle write requests efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If nonvolatile random access memory (NVRAM) is used to provide persistent storage, then data persistence is improved, but memory access latency becomes nondeterministic
Solution Approach 1:
The memory system is segmented into two distinct parts: a volatile DRAM cache for fast deterministic access and a nonvolatile NVRAM storage for persistent storage. This segmentation allows the system to exploit the speed of DRAM for frequently accessed data while maintaining the persistence benefits of NVRAM, thereby resolving the contradiction between data persistence and deterministic access latency.
Solution Approach 2:
A volatile DRAM cache acts as an intermediary between the host processor and the nonvolatile NVRAM storage. The cache buffer temporarily holds data that needs to be accessed frequently, providing deterministic access times for the processor while the slower NVRAM handles persistent storage in the background. This intermediary layer shields the processor from the nondeterministic latency of direct NVRAM access.
2Loss of time
If volatile DRAM is used for memory access, then deterministic access latency is achieved, but data persistence is lost during power interruptions
Solution Approach 1:
Data is preliminarily loaded from nonvolatile NVRAM storage into volatile DRAM cache before the host processor needs to access it. This preliminary action ensures that when the processor requests data, it is already present in the fast DRAM cache, providing deterministic access latency. Simultaneously, the data remains persistently stored in NVRAM, preventing data loss during power interruptions.
Solution Approach 2:
The volatile DRAM cache serves as an intermediary that temporarily holds copies of data from NVRAM. This intermediary allows the system to enjoy the speed of DRAM for active data while the NVRAM maintains the master copy for persistence, effectively resolving the contradiction between fast access and data persistence.
3Speed
If a cache is incorporated to reduce memory access latency, then access speed is improved, but the range of possible response latencies increases
Solution Approach 1:
The system applies local quality by providing different access characteristics for different data locations. Frequently accessed data resides in the fast DRAM cache with deterministic low latency, while less frequently accessed data remains in NVRAM. The cache coherence protocol ensures that the processor always accesses data from the appropriate location, maintaining predictable performance for cached data while allowing variability only for cache miss cases.
Data Source
AI summary
A memory module includes a memory, a cache to cache copies of information stored in the memory, and a controller. The controller is configured to access first data from the memory or the cache in response to receiving a read request from a processor. The controller is also configured to transmit a first signal a first nondeterministic time interval after receiving the read request. The first signal indicates that the first data is available. The controller is further configured to transmit a second signal a first deterministic time interval after receiving a first transmit request from the processor in response to the first signal. The second signal includes the first data. The memory module also includes a buffer to store a write request until completion and a counter that is incremented in response to receiving the write request and decremented in response to completing the write request.