NVDIMM Cache Controller Parallel Tag Checking
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Solution Overview
Problem
Traditional non-volatile dual in-line memory modules (NVDIMM) systems exhibit inefficiencies in data transfer and memory recall due to centralized control and buffering, leading to high access latency and lower bandwidth.
Innovation Solution
Implementing a hybrid memory module with a cache controller, multiplexing data buffers, and volatile and non-volatile memory, where the cache controller enables parallel tag checking and data movement operations, offloading cache control from the processor to improve efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a centralized controller and centralized buffer are used in NVDIMM systems, then the system structure is simplified and easier to manage, but data transfer efficiency decreases and access latency increases
Solution Approach 1:
The patent divides the centralized controller into multiple distributed cache controllers, each responsible for specific cache lines. This segmentation allows parallel processing of multiple memory operations simultaneously, improving data transfer efficiency while maintaining manageable system complexity through modular architecture.
Solution Approach 2:
The patent introduces a new architectural dimension by implementing distributed control at the cache line level rather than centralized control at the module level. This dimensional shift from centralized to distributed control enables concurrent operations across multiple cache controllers, resolving the contradiction between structural simplicity and operational efficiency.
2Device complexity
If a centralized controller is used to manage cache operations, then control logic is consolidated, but memory access latency increases due to sequential processing
Solution Approach 1:
The centralized control logic is segmented into multiple independent cache controllers distributed across different cache lines. Each cache controller can independently execute cache operations (read, write, invalidate) on its assigned cache lines, enabling parallel processing and significantly reducing access latency compared to sequential centralized processing.
Solution Approach 2:
Each cache controller is equipped with independent control logic that can autonomously manage its assigned cache lines without requiring centralized coordination. This self-service capability allows cache operations to proceed in parallel across multiple controllers, reducing overall access latency while maintaining consistent control through standardized protocols.
3Device complexity
If centralized buffering is implemented, then signal routing is simplified, but bandwidth is reduced due to bottleneck effects
Solution Approach 1:
The centralized buffer is segmented into multiple distributed buffers associated with individual cache controllers. This segmentation creates multiple parallel data pathways, eliminating the bandwidth bottleneck of centralized buffering while maintaining simplified routing through standardized interfaces between cache controllers and memory modules.
Data Source
AI summary
A high-performance on-module caching architecture for hybrid memory modules is provided. A hybrid memory module includes a cache controller, a first volatile memory coupled to the cache controller, a first multiplexing data buffer coupled to the first volatile memory and the cache controller, and a first non-volatile memory coupled to the first multiplexing data buffer and the cache controller, wherein the first multiplexing data buffer multiplexes data between the first volatile memory and the first non-volatile memory and wherein the cache controller enables a tag checking operation to occur in parallel with a data movement operation. The hybrid memory module includes a volatile memory tag unit coupled to the cache controller, wherein the volatile memory tag unit includes a line connection that allows the cache controller to store a plurality of tags in the volatile memory tag unit and retrieve the plurality of tags from the volatile memory tag unit.