NVDIMM Data Backup Encoding for Power Reduction
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Solution Overview
Problem
The existing NVDIMM data backup and recovery methods face challenges in reducing power consumption and time due to the increased storage overhead and power consumption associated with storing DBI information, which affects the capacity and reliability of supercapacitors and user experience.
Innovation Solution
A data backup method that encodes N-bit DQ and 1-bit DBI into N-bit Encoded Data Queue (EDQ) for storage in NAND flash memory, and a data recovery method that decodes EDQ back into DQ and DBI, optimizing the data written to NAND flash memory and reducing power consumption during both processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If DBI information is stored together with data backup in NAND flash memory, then the DRAM can retrieve correct data during recovery, but the storage space increases and the backup power consumption increases
Solution Approach 1:
The patent merges DBI information with data backup by encoding DBI into the least significant bit (LSB) of each byte in the data. This integration eliminates separate storage requirements and reduces overall data volume to be written to NAND flash, thereby reducing backup power consumption while maintaining data retrieval accuracy.
Solution Approach 2:
The patent changes the parameter representation of DBI information by encoding it within the data bytes themselves rather than storing it separately. This parameter transformation reduces the total data volume and minimizes the operational burden on the NAND flash interface during backup operations.
2Reliability
If DBI information is stored together with data backup in NAND flash memory, then the DRAM can retrieve correct data during recovery, but the data backup and recovery time increases
Solution Approach 1:
The patent combines DBI information with data backup into a single encoded data stream. This merging eliminates the need for separate read/write operations for DBI information, thereby reducing the total number of interface operations and shortening backup and recovery time.
Solution Approach 2:
The patent performs DBI encoding during the data backup process itself, preparing the encoded data in advance before writing to NAND flash. This preliminary encoding action streamlines the subsequent recovery process by eliminating the need for separate DBI information retrieval and processing steps.
3Use of energy by moving object
If the capacity of supercapacitors is increased to support higher power consumption during data backup, then the power consumption can be sustained, but the cost increases and reliability decreases
Solution Approach 1:
The patent changes the data representation parameters by encoding DBI within data bytes, which reduces the total data volume and consequently reduces the power consumption during backup operations. This allows the existing supercapacitor capacity to suffice without requiring larger, less reliable components.
Solution Approach 2:
The patent converts the potential harm of DBI storage overhead into benefit by efficiently integrating DBI encoding with data backup. This approach reduces the power consumption burden on supercapacitors, allowing the use of smaller, more reliable supercapacitor components with longer service lives.
Data Source
AI summary
The NVDIMM (200) comprises a DRAM (201), a NAND flash memory (202) and a NVDIMM controller (100), the NVDIMM controller (100) controlling the NVDIMM (200) and comprising a DDR controller (101), a NAND flash memory controller (102), a data backup module (103) and a data recovery module (104), and the DDR controller (101) using and enabling DBI. The backup method comprises: reading, by the DDR controller (101), N-bit DQ and 1-bit DBI from the DRAM (201) and sending the same to the data backup module; encoding, by the data backup module (103), the N-bit DQ and the 1-bit DBI into N-bit EDQ according to the values of the N-bit DQ and the 1-bit DBI, and sending the N-bit EDQ to the NAND flash memory controller; and receiving, by the NAND flash memory controller (102), the N-bit EDQ and writing the N-bit EDQ into the NAND flash memory (202).