NVDIMM Data Buffer Serial Transfer Mechanism
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Solution Overview
Problem
Current memory devices face challenges in efficiently transferring data between volatile and non-volatile memory modules, particularly during power loss scenarios, where data needs to be saved from volatile to non-volatile memory and vice versa, often resulting in latency and bandwidth limitations.
Innovation Solution
The implementation of a data buffer system within a dual in-line memory module (DIMM) that uses a sideband bus for serial data transfer between volatile and non-volatile memory devices, allowing them to operate at full speed without latency, and includes a multiplexor to select the appropriate data bus for efficient data routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is transferred directly between volatile and non-volatile memory devices using parallel buses, then transfer speed is improved, but device complexity and bandwidth limitations worsen
Solution Approach 1:
A data buffer is introduced as an intermediary component between volatile and non-volatile memory devices. The buffer receives data from volatile memory via a first bus and transfers it to non-volatile memory via a second bus, simplifying the routing architecture while maintaining transfer capability. This mediator approach resolves the contradiction by eliminating complex direct routing while preserving data transfer functionality.
Solution Approach 2:
The data transfer path is segmented into distinct stages: volatile memory to data buffer (first bus), and data buffer to non-volatile memory (second bus). This segmentation allows each bus to be optimized independently and reduces the overall system complexity by breaking down the complex direct transfer path into manageable segments.
2Device complexity
If a data buffer is introduced to simplify data routing, then device complexity is reduced, but transfer latency increases
Solution Approach 1:
The data buffer performs preliminary actions by receiving and holding data from volatile memory before the actual transfer to non-volatile memory begins. This allows the buffer to prepare data in advance, reducing the critical path latency during the actual transfer operation. The buffer can pre-process and stage data, so when transfer is needed, it can occur more quickly.
Solution Approach 2:
The data buffer maintains continuous operation by simultaneously receiving data from volatile memory and transferring it to non-volatile memory through pipelined operations. This continuity ensures that the buffer is always productive and does not create idle time, thereby minimizing the impact on overall transfer latency while maintaining simplified routing.
3Productivity
If volatile memory operates at full speed during data transfer, then productivity is improved, but data loss risk during power loss increases
Solution Approach 1:
The data buffer serves as a safety intermediary that can detect power loss conditions and initiate emergency data transfer to non-volatile memory. While volatile memory continues operating at full speed for normal productivity, the buffer monitors system status and can rapidly transfer critical data to non-volatile storage when power loss is detected, thus protecting against data loss without sacrificing normal operation speed.
Solution Approach 2:
The system performs preliminary actions by continuously monitoring power status and pre-positioning data in the buffer for rapid transfer. When power loss is anticipated or detected, the buffer can immediately initiate transfer to non-volatile memory without waiting for volatile memory operations to complete, thereby protecting data while maintaining normal high-speed operation during powered states.
Data Source
AI summary
The present disclosure includes apparatuses and methods related to a data buffer in a non-volatile dual in-line memory module (NVDIMM). An example apparatus can include a data buffer couplable to a host, a first memory device (e.g., volatile memory), wherein the first memory device is coupled to the data buffer via a first bus, a second memory device (e.g., non-volatile memory), and a controller, wherein the controller is coupled to the data buffer via a second bus and wherein the controller is configured to cause a data transfer from first memory device to the second memory device via the data buffer and the second bus.