NVDIMM Dual I/O Port Multiplexer for DRAM-NVM Data Path Optimization
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Solution Overview
Problem
As data processing in computing systems increases, data bottlenecks occur due to the mismatch between data throughput and communication speed of interfaces connected to SSD devices, leading to performance deterioration in computing systems.
Innovation Solution
A nonvolatile dual in-line memory module (NVDIMM) is introduced, featuring a dynamic random access memory (DRAM) with dual input/output ports, allowing for selective port usage based on transfer modes to optimize data exchange between DRAM, NVM, and external devices, enabling simultaneous data transfer and bypass operations to enhance performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data throughput is increased to support larger capacity processing, then data processing efficiency is improved, but communication speed bottleneck occurs due to interface limitations
Solution Approach 1:
The system segments data transfer paths into multiple independent channels: a first path for host-DRAM communication and a second path for DRAM-NVM communication. This segmentation allows simultaneous data operations without interference, resolving the bottleneck by enabling parallel data processing through separate communication pathways.
Solution Approach 2:
The patent introduces a new dimensional approach by implementing dual I/O ports on the DRAM device, creating additional communication dimensions. The first I/O port handles host interactions while the second I/O port handles NVM interactions, allowing multi-dimensional data flow that eliminates the single-path bottleneck.
2Productivity
If dual I/O ports are implemented in DRAM, then data transfer capability is improved, but device complexity increases
Solution Approach 1:
The DRAM device is designed with multi-functionality, where the same DRAM structure serves multiple purposes: it acts as both the primary memory for host access and as an intermediary buffer for NVM data transfer. The dual I/O ports enable the DRAM to perform both host communication and NVM communication functions simultaneously without requiring separate dedicated hardware for each function.
Solution Approach 2:
The DRAM device functions as an intermediary between the host and NVM, utilizing its dual I/O ports to mediate data transfer operations. The first I/O port interfaces with the host while the second I/O port interfaces with the NVM, allowing the DRAM to coordinate data flow between different systems without requiring complex integrated architecture.
3Device complexity
If sequential port usage is used, then device complexity is reduced, but data processing efficiency deteriorates due to bottleneck
Solution Approach 1:
The system maintains continuous useful action by enabling simultaneous data operations through independent ports. While the first I/O port handles host read/write operations, the second I/O port concurrently handles NVM data transfer, ensuring that data processing continues without interruption or waiting, thereby eliminating efficiency bottlenecks.
Solution Approach 2:
The patent implements dynamic port selection and simultaneous operation capabilities. The system can dynamically route data through different ports based on operational needs, allowing flexible and adaptive data transfer patterns that optimize performance while managing complexity through intelligent control rather than fixed architecture.
Data Source
AI summary
A method is for operating a nonvolatile dual in-line memory module (NVDIMM). The NVDIMM includes a dynamic random access memory (DRAM) and a nonvolatile memory (NVM) device, the DRAM including a first input/output (I/O) port and a second I/O port, and the second I/O port connected to the NVM device. The method includes receiving an externally supplied command signal denoting a read/write command and a transfer mode, driving a multiplexer to select at least one of the first and second I/O ports according to the transfer mode of the command signal, and reading or writing data according to the read/write command of the command signal in at least one of the DRAM and NVM device using the at least one of the first and second I/O ports selected by driving the multiplexer.