Multi-Processor Firmware Boot via NVDIMM Segmentation
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Solution Overview
Problem
Conventional computing devices with multiple processors face significant booting delays due to reliance on a single SPI flash chip, where only directly connected processors can fetch firmware directly, causing other processors to wait and reboot through intermediate links.
Innovation Solution
Implementing a method where each CPU has a firmware region in main memory, allowing firmware to be copied from a firmware reservoir to these memory regions for faster access, and using persistent memory regions like NVDIMM for storing firmware images, which provides faster access speeds and protects integrity with passphrases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a single SPI flash chip is used for firmware storage, then device complexity is reduced, but booting time increases significantly for non-direct-connected processors
Solution Approach 1:
The patent divides the single firmware storage resource into multiple distributed firmware regions, with each CPU having its own dedicated firmware region in main memory. This segmentation allows each processor to access firmware independently without waiting for other processors, directly resolving the booting time delay issue while distributing the complexity across multiple memory regions rather than concentrating it in a single SPI flash access bottleneck.
Solution Approach 2:
The patent implements preliminary action by pre-copying firmware images from the SPI flash chip to main memory firmware regions during system initialization or firmware update operations. This advance preparation ensures that when booting occurs, all CPUs have their firmware already available in fast memory, eliminating the need for time-consuming firmware fetching during the actual boot process.
2Speed
If firmware is stored in main memory instead of SPI flash, then firmware access speed increases, but data integrity protection becomes more challenging
Solution Approach 1:
The patent introduces an intermediary mechanism in the form of cryptographic authentication and verification protocols that mediate between the fast main memory storage and the reliability requirement. Firmware images are signed and verified using cryptographic keys, creating a trust chain that ensures integrity without sacrificing the speed advantage of main memory access. This intermediary verification layer resolves the contradiction by adding security checks that operate transparently during the fast boot process.
3Ease of operation
If all CPUs fetch firmware directly from SPI flash, then firmware access is simplified, but only directly connected processors can boot, causing delays for other processors
Solution Approach 1:
The patent transitions from a single-dimension firmware access model (all CPUs accessing SPI flash through a hierarchical bus structure) to a multi-dimensional model where each CPU has direct access to firmware in its own memory region. This dimensional change in the storage architecture allows parallel firmware loading across all processors simultaneously, transforming the sequential bottleneck into a parallel operation that dramatically improves multi-processor booting efficiency.
Data Source
AI summary
A method for preparing fast boot of an information handling apparatus. The information handling apparatus contains a first CPU configured to connect to a storage device storing firmware and a second CPU connected to the first CPU. The method contains the steps of: allocating a firmware region in memories associated with each one of the first and second CPUs respectively; and copying a firmware from a storage device to the firmware region of each one of the memories. By utilizing a system memory such as NVDIMM which provides higher access speed than NAND flash and also persistent data storage, one or more CPUs can be booted from firmware images in the NVDIMM much faster, thus saving the total booting time.