NVDIMM Memory Module Layout Optimization for Capacity
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Solution Overview
Problem
NVDIMM-N memory modules face a challenge of insufficient capacity due to the space occupied by the NVDIMM controller and flash memory cells, which reduces the available area for DRAM cells.
Innovation Solution
The memory module design includes a control chip, data flash memory chips, memory cells, and non-volatile memory, where the control chip sends control commands to perform data processing between memory cells and non-volatile memory, optimizing the layout to reduce connection lines and increase the area available for memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the NVDIMM controller and flash memory cells are included for power failure protection, then data security and reliability are improved, but the available area for DRAM cells is reduced, resulting in insufficient memory capacity
Solution Approach 1:
The patent segments the memory module into distinct functional areas: a first memory region for volatile memory cells and a second memory region for non-volatile memory cells. This spatial segmentation allows both types of memory to coexist without one encroaching on the other's area, resolving the contradiction between reliability (needing non-volatile memory) and capacity (needing volatile memory area).
Solution Approach 2:
The patent transitions from a single-plane memory architecture to a multi-plane architecture where volatile and non-volatile memory cells are arranged in different regions or layers. This dimensional reorganization allows the controller to manage both memory types independently, maximizing the use of available space while maintaining data security through non-volatile storage.
2Reliability
If the NVDIMM controller manages both DRAM and flash memory, then power failure protection is achieved, but the controller and flash memory occupy space that could be used for DRAM cells
Solution Approach 1:
The patent merges the volatile and non-volatile memory systems into a single unified memory module with a common controller. This integration allows the controller to manage both memory types through standardized interfaces, reducing the need for separate control circuits and minimizing the space occupied by control infrastructure.
Solution Approach 2:
The controller is designed with multi-functionality to handle both volatile and non-volatile memory operations, including data writing, reading, and power failure protection. This universal controller reduces the overall device complexity by eliminating the need for separate specialized controllers for each memory type.
3Loss of information
If flash memory cells are used for data backup, then data loss is prevented during power failure, but the capacity of the memory module is reduced
Solution Approach 1:
The system performs preliminary data backup by automatically copying data from volatile memory to non-volatile memory regions before power failure occurs. This preliminary action ensures data security without requiring a separate dedicated backup area, as the non-volatile region serves dual purposes: permanent storage and emergency backup.
Solution Approach 2:
The patent implements a data recovery mechanism where data is discarded from volatile memory after successful transfer to non-volatile memory, or recovered from non-volatile memory after power restoration. This discarding and recovering process maximizes the effective capacity by reuse of the volatile memory region while maintaining data security through non-volatile storage.
Data Source
AI summary
A memory module is provided. The memory module includes: a control chip, at least one data flash memory chip, at least two memory cells, and at least one non-volatile memory, each of the at least one data flash memory chip is connected to at least one of the at least two memory cells and at least one of the at least one non-volatile memory, the control chip is connected to the at least one data flash memory chip and the at least two memory cells, and the memory is further connected to at least one capacitor; the control chip is configured to send a control command; and each of the at least one data flash memory chip is configured to perform, based on the control command from the control chip, data processing between the memory cell connected thereto and the non-volatile memory connected thereto.