NVDIMM-P Memory Controller Write Group Tables

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Solution Overview

Problem

Existing memory controllers for Non-Volatile Dual In-line Memory Modules with Persistent memory (NVDIMM-P) face inefficiencies in managing data between volatile and non-volatile portions, particularly in identifying and flushing cache lines to non-volatile memory, leading to increased latency and computational overhead.

Innovation Solution

The implementation of a memory controller with a first write group table and a second write group table, along with cache metadata, allows for efficient tracking and flushing of data by using a persist flag and metadata states to determine whether data needs to be written to non-volatile memory, reducing the need for scanning the entire volatile memory and minimizing redundant writes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the memory controller scans the entire volatile memory to identify cache lines for flushing, then data persistence is ensured, but computational overhead and latency increase

Engineering Contradiction:
Improvedata persistenceVSAvoidcomputational overhead
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent divides the volatile memory into multiple buffers, each associated with a specific write group identifier. The memory controller maintains a write group table that maps write group identifiers to their corresponding buffers, enabling targeted flushing of only the affected buffer instead of scanning the entire volatile memory. This segmentation approach ensures data persistence for the relevant data while significantly reducing computational overhead.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a write group table as an intermediary data structure between the volatile memory and non-volatile memory. This table maintains metadata about which buffers contain data that needs to be flushed, serving as a mediator that eliminates the need for full memory scans. The write group table stores mappings between write group identifiers and buffer locations, enabling efficient identification of data requiring persistence.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If the memory controller uses multiple write group tables to track cache lines, then flushing efficiency improves, but device complexity increases

Engineering Contradiction:
Improveflushing efficiencyVSAvoiddevice complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent implements a memory controller with multiple write group tables that serve multiple functions: tracking which buffers need flushing, mapping write group identifiers to buffer locations, and managing the flushing process. By making these data structures multi-functional, the system achieves efficient flushing without requiring separate dedicated hardware components for each function, thereby limiting the increase in device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If the memory controller writes all data to non-volatile memory, then data persistence is maximized, but write operations and latency increase

Engineering Contradiction:
Improvedata persistenceVSAvoidlatency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies local quality by flushing data to non-volatile memory selectively based on write group identifiers rather than flushing all data uniformly. Each buffer is associated with specific write group identifiers, and the memory controller flushes only the buffers corresponding to active write groups. This localized flushing approach maximizes data persistence for relevant data while minimizing unnecessary write operations and reducing latency.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS11175853B2Systems and methods for write and flush support in hybrid memory
Publication Date: 2021.11.16 SAMSUNG ELECTRONICS CO LTD
  • US11175853B2 patent drawing
  • US11175853B2 patent drawing
  • US11175853B2 patent drawing

AI summary

A memory module includes a memory controller including: a host layer; a media layer coupled to a non-volatile memory; and a logic core coupled to the host layer, the media layer, and a volatile memory, the logic core storing a first write group table including a plurality of rows, and the logic core being configured to: receive a persistent write command including a cache line address and a write group identifier; receive data associated with the persistent write command; write the data to the volatile memory at the cache line address; store the cache line address in a selected buffer of a plurality of buffers in a second write group table, the selected buffer corresponding to the write group identifier; and update a row of the first write group table to identify locations of the selected buffer containing valid entries, the row corresponding to the write group identifier.