NVDIMM Parallel Architecture for Bandwidth and Layout Constraints
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Solution Overview
Problem
Current NVDIMM designs face layout design constraints due to wire clogging and performance degradation from limited FPGA I/Os, which restrict data transfer bandwidth and efficiency, especially when accessing slower storage devices.
Innovation Solution
Implementing a parallel architecture with multiple interface bridge chips to facilitate parallel data transfer between the memory data bus and non-volatile memory, synchronized by a bridge controller for orderly operations, allowing independent access to multiple NVMs and DRAM chips, thereby alleviating layout constraints and enhancing data transfer efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single FPGA is used to facilitate data transfer from memory data bus to on-board NAND Flashes, then the layout design is simplified, but wire clogging occurs in PCB layout and performance degrades due to limited I/Os
Solution Approach 1:
The patent divides the single FPGA into multiple interface bridge chips, each handling a subset of data bits. This segmentation allows parallel data transfer paths, eliminating wire clogging while maintaining layout simplicity. Each bridge chip connects to separate NVM chips, enabling independent data transfer operations and increasing overall bandwidth.
2Device complexity
If a single FPGA is used for data transfer, then hardware cost is reduced, but data transfer bandwidth is limited by FPGA I/O constraints
Solution Approach 1:
The single FPGA is segmented into multiple interface bridge chips, each with dedicated I/Os for specific data bit groups. This allows the system to utilize multiple parallel data transfer channels, overcoming the I/O limitations of a single FPGA while maintaining configuration simplicity through modular design.
Solution Approach 2:
The patent transitions from a single-series data transfer path to a parallel multi-dimensional architecture. Multiple interface bridge chips operate simultaneously on different data bit groups, effectively adding a temporal and spatial dimension to data transfer operations, thereby increasing bandwidth without increasing single-component complexity.
3Productivity
If full width memory data bus transfers through a single FPGA in one transaction cycle, then data transfer efficiency is maximized, but layout design constraints require thicker PCB or more routing layers
Solution Approach 1:
The full width memory data bus is segmented into multiple smaller data bit groups, each handled by a separate interface bridge chip. This segmentation allows each chip to have dedicated, localized routing paths, eliminating the need for complex global routing and thicker PCB while maintaining full bandwidth efficiency through parallel operations.
Data Source
AI summary
A non-volatile dual-in-line memory module (NVDIMM) with a parallel architecture is described. It enables parallel access to on-board nonvolatile memory (NVM) to improve storage throughput and to alleviate layout design constraints.