NV-DIMM Storage System with SNVRAM Protocol and Command Buffer
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Solution Overview
Problem
Existing standards for DRAM-based DIMMs are not suitable for NV-DIMMs due to non-deterministic read and write operations, which can cause delays exceeding specified times, leading to inefficiencies and potential data loss in non-volatile memory systems.
Innovation Solution
The implementation of a SNVRAM protocol that allows for non-deterministic read and write operations, enabling NV-DIMMs to perform time-consuming actions like wear leveling and error correction without adhering to strict time constraints, and using a command and address buffer to synchronize data flow and manage bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If NV-DIMMs use non-volatile memory devices instead of DRAM chips, then data retention is improved, but read and write operation times become non-deterministic and may exceed specified times
Solution Approach 1:
The patent segments the memory system into multiple independent non-volatile memory devices, each capable of handling operations independently. This segmentation allows the system to perform wear leveling and error correction on individual devices without blocking other operations, thereby reducing overall operation time while maintaining data retention benefits
Solution Approach 2:
The patent implements preliminary actions by performing wear leveling and error correction operations before they are critically needed. The controller proactively manages non-volatile memory devices by redistributing data wear and correcting errors in advance, which prevents operation delays during critical read/write operations while preserving data integrity
2Reliability
If NV-DIMMs perform wear leveling and error correction operations, then data integrity is improved, but operation delays increase
Solution Approach 1:
The patent ensures continuity of useful action by implementing background wear leveling and error correction operations that run concurrently with normal read/write operations. The controller continuously manages non-volatile memory devices without interrupting user operations, thereby maintaining data integrity while minimizing operation delays
Solution Approach 2:
The patent introduces a controller as an intermediary between the host and non-volatile memory devices. This intermediary manages wear leveling and error correction operations transparently, shielding the host from operation delays while ensuring data integrity through proactive memory management
3Speed
If DRAM-based DIMMs are used, then fast access times are achieved, but power consumption increases and cost per gigabyte is higher
Solution Approach 1:
The patent changes the fundamental parameter of memory volatility by transitioning from volatile DRAM to non-volatile memory devices. This parameter change enables the system to achieve comparable access times while dramatically reducing power consumption, as non-volatile memory devices do not require continuous power to maintain data state
Solution Approach 2:
The patent adopts non-volatile memory devices that are more cost-effective per gigabyte compared to DRAM chips. Although individual non-volatile memory devices may have shorter operational lifetimes than DRAM, the lower cost and reduced power consumption make them economically advantageous for capacity-intensive applications
Data Source
AI summary
A storage system with several integrated components and method for use therewith are provided. In one embodiment, a storage system comprising: a plurality of non-volatile memory devices; a controller in communication with the plurality of non-volatile memory devices; a plurality of data buffers in communication with the controller and configured to store data sent between the controller and an input/output bus; and a command and address buffer configured to store commands and addresses sent from a host, wherein the command and address buffer is further configured to synchronize data flow into and out of the plurality of data buffer; wherein at least three of the above components are integrated with each other.