nvDRAM Integration with Isolation Devices for Bit-Line Control
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Solution Overview
Problem
Current system architectures that utilize both volatile and non-volatile memory devices separately consume large area and reduce data transfer speed between static random-access memory (SRAM) and non-volatile memory (NVM).
Innovation Solution
A multi-bit non-volatile dynamic random access memory (nvDRAM) device is introduced, which combines DRAM and NVM arrays with isolation devices to control bit line connections, allowing for efficient data transfer and reduced power consumption by implementing switch devices between DRAM and NVM arrays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If volatile memory (SRAM/DRAM) and non-volatile memory (NVM) are implemented as separate devices, then each memory type can be optimized independently, but large area is consumed and data transfer speed is reduced
Solution Approach 1:
The patent combines DRAM and NVM into a single integrated memory device with a unified array layout. The DRAM array and NVM array are positioned adjacent to each other within the same device, sharing common bit lines and word lines. This merging eliminates the need for separate memory devices while maintaining the ability to independently access and optimize each memory type, directly resolving the contradiction between independent optimization and area consumption.
2Ease of manufacture
If volatile memory (SRAM/DRAM) and non-volatile memory (NVM) are implemented as separate devices, then each memory type can be optimized independently, but data transfer speed is reduced
Solution Approach 1:
The integrated memory device merges DRAM and NVM arrays with shared bit lines and word lines, enabling direct data transfer between memory types without external interfacing. The common bit lines allow simultaneous access to both DRAM and NVM cells, dramatically increasing data transfer speed while maintaining independent optimization capabilities through selective word line activation.
Solution Approach 2:
The shared bit lines act as intermediaries between the DRAM array and NVM array, facilitating rapid data transfer. When data needs to be transferred between memory types, the common bit lines provide a direct communication path, eliminating the need for complex external interfaces and improving transfer speed while preserving independent memory optimization.
3Area of stationary object
If DRAM and NVM arrays are integrated with shared bit lines, then area is reduced and data transfer speed is improved, but DRAM bit-line loading increases
Solution Approach 1:
The patent implements dynamic control of bit line sharing through selective word line activation. The isolation devices (transistors) are dynamically switched based on which memory array is being accessed. When the DRAM array is accessed, the isolation devices connect the DRAM bit lines to the DRAM array and disconnect from the NVM array, preventing NVM cells from loading the DRAM bit lines. This dynamic switching resolves the contradiction by enabling area-efficient integration while maintaining low bit-line loading during operations.
4Area of stationary object
If DRAM and NVM arrays are integrated with shared bit lines, then area is reduced and data transfer speed is improved, but device complexity increases
Solution Approach 1:
The shared bit lines serve multiple functions: they act as bit lines for the DRAM array, bit lines for the NVM array, and as isolation control lines through the integrated transistors. This multi-functionality reduces the total number of separate wiring structures needed, thereby reducing area while the systematic design of the isolation devices manages the added complexity in a controlled manner.
Data Source
AI summary
Technologies for a multi-bit non-volatile dynamic random access memory (nvDRAM) device, which may include a DRAM array having a plurality of DRAM cells with single or dual transistor implementation and a non-volatile memory (NVM) array having a plurality of NVM cells with single or dual transistor implementations, where the DRAM array and the NVM array are arranged by rows of word lines and columns of bit lines. The nvDRAM device may also include one or more of isolation devices coupled between the DRAM array and the NVM array and configured to control connection between the dynamic random access bit lines (BLs) and the non-volatile BLs. The word lines run horizontally and may enable to select one word of memory data, whereas bit lines run vertically and may be connected to storage cells of different memory address.