NVDRAM Cell With Programming Line For Compact Memory
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Solution Overview
Problem
Existing non-volatile dynamic random access memories (NVDRAMs) face challenges in efficiently combining non-volatile and dynamic RAM characteristics on integrated circuits, requiring a compact design that effectively achieves desired operating characteristics without excessive space.
Innovation Solution
A non-volatile dynamic random access memory cell design featuring a capacitor coupled to a storage node between a transistor and a series combination of a non-volatile element and another transistor, with specific circuitry for row and column operations, allowing for efficient reading, writing, storing, and restoring logic states using both DRAM and NVM functionalities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If DRAM cells are used to provide RAM characteristics on the same integrated circuit as NVM cells, then the memory size is reduced, but the complexity of arranging and operating the combined memory structure increases
Solution Approach 1:
The memory array is segmented into distinct DRAM cells and NVM cells with separate access mechanisms. DRAM cells use bit lines for fast read/write operations while NVM cells use programming lines for non-volatile storage. This segmentation allows each cell type to operate independently according to its characteristics, reducing the overall complexity of managing the hybrid structure.
Solution Approach 2:
The integrated circuit design makes the memory structure universal by enabling the same physical memory array to serve multiple functions: volatile RAM operations through DRAM cells and non-volatile storage through NVM cells. The control circuitry is designed to selectively activate different cell types based on operational requirements, allowing a single memory structure to provide both fast access and persistent storage capabilities.
2Ease of operation
If SRAM cells are used in combination with NVM cells, then the interface with NVM feature is simplified, but the memory size increases
Solution Approach 1:
The patent merges DRAM cells and NVM cells into a unified memory array structure where both cell types share common access pathways and control mechanisms. This merging approach allows the system to maintain interface simplicity while using the more space-efficient DRAM cell structure rather than SRAM cells, thereby reducing overall memory size.
3Quantity of substance
If general purpose DRAM is used on the integrated circuit, then the memory density is improved, but the challenge of achieving desired operating characteristics without excessive space increases
Solution Approach 1:
Different regions of the memory array are assigned different qualities: DRAM cells provide high-speed access for frequently accessed data, while NVM cells provide persistent storage for less frequently accessed data. The control circuitry applies local quality by selectively activating different cell types based on the specific operational requirements, allowing the system to achieve desired operating characteristics without requiring excessive space.
Data Source
AI summary
A memory circuit includes a first bit line, a second bit line, and a memory cell that is coupled to first bit line and the second bit line. The memory cell includes a capacitor, a first pass gate transistor, a non-volatile (NV) element, and a second pass gate transistor. The first capacitor has a first terminal coupled to a first storage node and a second terminal coupled to a reference. The first pass gate transistor is coupled between the first bit line and the first storage node. The NV element and a second pass gate transistor are coupled in series, wherein the first NV element and the second pass gate transistor are coupled between the first storage node and the first program line.