Non-Volatile Flip-Flop Circuit for Intermittent Processor Resume
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Solution Overview
Problem
Conventional processor-based devices incur a disproportionate burden of power-on or boot sequences during intermittent operation, necessitating repetitive save and restore cycles to non-volatile memory, which is inefficient and power-consuming.
Innovation Solution
Implementing a non-volatile flip flop (NVFF) in critical registers and memory structures to retain processing state during power down, allowing seamless resume upon power restoration without the need for reboot or data transfer to external storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional processor operation is used with full boot cycles, then processing state is reliably initialized, but power consumption and time overhead increase significantly during intermittent operation
Solution Approach 1:
The processor state is segmented into critical components that require persistence (registers, memory structures) and non-critical components that can be reinitialized. Only the essential state elements are preserved across power cycles, allowing the system to skip full boot sequences while maintaining reliability for intermittent operation
Solution Approach 2:
The system performs preliminary saving of critical processor state to non-volatile memory before power down, and preliminary restoration of this state upon power up. This preliminary action eliminates the need for full boot cycles during intermittent operation, reducing power consumption while ensuring reliable state recovery
2Reliability
If full boot cycles are performed at each power-on, then complete system initialization is achieved, but time overhead and productivity decrease during intermittent computing
Solution Approach 1:
The essential processor state information is extracted from the full system state and stored separately in non-volatile memory. This extraction allows the system to recover only the critical state elements upon power up, eliminating the time-consuming portions of full boot cycles while maintaining reliable initialization of essential components
Solution Approach 2:
The system performs preliminary capture of processor state before power down and preliminary restoration upon power up. This preliminary action enables the system to bypass lengthy boot sequences during intermittent operation, significantly reducing time overhead while ensuring complete initialization of critical system components
3Reliability
If data is repeatedly saved to and restored from external storage, then processing state is preserved, but device complexity and operational overhead increase
Solution Approach 1:
The non-volatile memory structure is merged directly with the processor circuitry, eliminating the need for separate external storage devices. This integration allows critical processor state to be saved and restored within the processor itself, reducing device complexity and operational overhead while maintaining reliable state preservation across power cycles
Solution Approach 2:
A non-volatile bit structure acts as an intermediary between volatile processor registers and external non-volatile memory. This intermediary enables direct state persistence within the processor without requiring complex external storage interfaces, reducing hardware overhead while ensuring reliable state preservation
Data Source
AI summary
A non-volatile flip flop (NVFF) incorporates a non-volatile bit into important registers and memory structures to allow a processing state to be resumed after a power down without the need to reboot or write state data to disk. An intermittent computing device, designed for periodic, rather than constant, operation, can benefit by avoiding the need to incur a formal shutdown and writing of data to disk or non-volatile memory. Similarly, no boot or reading of state data need occur when a subsequent intermittent computing cycle occurs. Flip-flop structures that store data bits employ the NVFF capability, typically amounting to around 20% of the total number of gates in the intermittent computing device. Accordingly, the number of power consuming elements is only modestly increased, and savings achieved by avoiding the need to write state data to disk or non-volatile memory.