NVL Array Parity Checking for Zero-Leakage State Retention
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Solution Overview
Problem
Existing portable electronic devices face challenges in reducing leakage current during standby power mode, requiring continuous power to retain state information, which is inefficient for battery-operated devices and energy harvesting applications.
Innovation Solution
The implementation of nonvolatile logic (NVL) using ferroelectric random access memory (FRAM) to store the state of flip-flops, allowing complete power removal without data loss, with NVL arrays dispersed throughout the logic cloud and controlled by a central NVL controller, enabling instant-on capability and zero leakage in sleep mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If shadow latch is used to retain state information during standby power mode, then data retention is improved, but leakage current is reduced only partially and some power is still required
Solution Approach 1:
The patent extracts the state retention function from the traditional shadow latch circuit and relocates it to a separate nonvolatile memory array. This allows the main logic circuit to be completely powered down while state information is preserved externally in the nonvolatile memory, achieving zero leakage current while maintaining data retention.
Solution Approach 2:
The patent introduces a nonvolatile memory array as an intermediary between the logic circuit and state retention. This intermediary stores state information when the logic circuit is powered down and restores it upon power-up, eliminating the need for continuous power to the retention circuit while ensuring data persistence.
2Loss of energy
If nonvolatile logic using FRAM is implemented, then zero leakage operation in sleep mode is achieved, but system complexity increases due to NVL arrays and central controller
Solution Approach 1:
The nonvolatile memory array serves multiple functions: it acts as a shadow latch for state retention, provides instant-on capability by preserving system state, and enables complete power removal without data loss. This multi-functionality justifies the added complexity by eliminating the need for separate retention circuits and reducing overall power consumption.
Solution Approach 2:
The patent changes the operational parameters of the memory system by using nonvolatile FRAM technology with different power characteristics. The FRAM cells can maintain their state with zero power consumption, allowing the system to operate in a complete power-down mode rather than requiring standby power for retention circuits.
3Reliability
If parity bit is calculated and stored with each row of data, then error detection capability is improved, but memory array area increases
Solution Approach 1:
The patent implements partial error detection by adding only a single parity bit for each row of data bits. This provides basic error detection capability without the overhead of more comprehensive error correction codes, achieving a balance between reliability improvement and area overhead.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution allows for zero-leakage operation in sleep mode and rapid system state restoration upon power-up, reducing energy consumption and eliminating the need for continuous power to retain state information, making it suitable for energy harvesting applications and handheld devices with limited resources.
Implementation Method 1
The implementation of nonvolatile logic (NVL) using ferroelectric random access memory (FRAM) to store the state of flip-flops
Data Source
AI summary
A system on chip (SoC) has a nonvolatile memory array of n rows by m columns coupled to one or more of the core logic blocks. M is constrained to be an odd number. Each time a row of m data bits is written, parity is calculated using the m data bits. Before storing the parity bit, it is inverted. Each time a row is read, parity is checked to determine if a parity error is present in the recovered data bits. A boot operation is performed on the SoC when a parity error is detected.