NVL Array Wakeup Sequencing for Zero-Leakage State Retention

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Solution Overview

Problem

Existing portable electronic devices face challenges in reducing leakage current during standby power mode, requiring constant power to retain state information, which is inefficient for battery-operated devices and energy harvesting applications.

Innovation Solution

The implementation of non-volatile logic (NVL) in System on Chip (SoC) using ferroelectric random access memory (FRAM) allows for zero leakage in sleep mode and rapid system state restoration, eliminating the need for constant power by dispersing NVL arrays throughout the logic cloud and utilizing a central NVL controller for state management.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If shadow latch is used to retain state information during standby power mode, then data retention is improved, but leakage current is reduced only partially and additional power supply circuits are required

Engineering Contradiction:

Improvedata retentionVSAvoidleakage current

Core Design Contradiction:

ReliabilityVSLoss of energy

Solution Approach 1:

The patent extracts the state retention function from the traditional shadow latch circuit and relocates it to non-volatile memory cells. This removes the need for continuous power supply to retention circuits, as the non-volatile memory inherently retains state without power, thereby eliminating leakage current associated with shadow latch operation.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent changes the fundamental parameter of state retention from volatile (requiring continuous power) to non-volatile (retaining state without power). By using non-volatile memory cells with different retention characteristics, the system achieves state retention with zero leakage current during standby mode.

Inventive Principle:

Principle #35Parameter changes

2Loss of energy

If thick gate oxide transistors and high threshold voltage transistors are used in shadow latch, then leakage current is reduced, but system performance deteriorates when shadow latch is detached from rest of circuit

Engineering Contradiction:

Improveleakage currentVSAvoidsystem performance

Core Design Contradiction:

Loss of energyVSProductivity

Solution Approach 1:

The patent creates a copy of the state information in non-volatile memory cells that can be rapidly restored to the main logic circuit. This copying mechanism allows the shadow latch to remain detached during standby (saving energy) while enabling fast restoration of system state, thus maintaining productivity without the performance penalty of detached shadow latches.

Inventive Principle:

Principle #26Copying

3Use of energy by moving object

If energy harvesting is used to provide power, then portable device operation is enabled, but available power is very small and intermittent

Engineering Contradiction:

Improvepower availabilityVSAvoidpower magnitude

Core Design Contradiction:

Use of energy by moving objectVSPower

Solution Approach 1:

The patent performs preliminary action by capturing and storing system state information in non-volatile memory cells before power is completely removed. This allows the device to maintain state information through intermittent power availability, enabling rapid resumption of operation when power becomes available again without requiring full system reboot.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent enables periodic operation where the system can enter low-power states during intermittent power availability and rapidly reactivate when power is restored. The non-volatile memory maintains state information through these periodic power interruptions, allowing the device to operate effectively with energy harvesting sources that provide intermittent rather than continuous power.

Inventive Principle:

Principle #19Periodic action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables portable devices to maintain state without continuous power, reducing energy consumption and enabling instant-on capabilities, suitable for energy harvesting applications where intermittent power is available.

Implementation Method 1

The implementation of non-volatile logic (NVL) in System on Chip (SoC) using ferroelectric random access memory (FRAM) allows for zero leakage in sleep mode

Methodology Applied

Scientific EffectFerroelectric effect:

Data Source

PatentUS9711196B2Configuration bit sequencing control of nonvolatile domain and array wakeup and backup

Publication Date: 2017.07.18 TEXAS INSTRUMENTS INC

AI summary

A processing device includes a plurality of non-volatile logic element array domains having two or more non-volatile logic element arrays to store 2006 a machine state of the processing device stored in a plurality of volatile store elements. Configuration bits are read to direct which non-volatile logic element array domains are enabled first and to direct an order in which the first enabled non-volatile logic element array domains are restored or backed up in response to entering a wakeup or backup mode. Configuration bits can be read to direct an order of and a parallelism of how individual non-volatile logic element arrays in a first enabled non-volatile logic element array domain are restored or backed up. The order of restoration or backing up can be controlled by instructions from non-volatile arrays of the first enabled of the plurality of non-volatile logic element array domains.