Nonvolatile Logic Array Backup Prioritization for Standby Power Loss
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Solution Overview
Problem
Existing portable electronic devices face challenges in reducing leakage current during standby power mode, requiring continuous power to retain state information, which is inefficient for battery-operated devices and energy harvesting applications.
Innovation Solution
The implementation of non-volatile logic (NVL) within System on Chip (SoC) using ferroelectric random access memory (FRAM) allows for complete removal of power without losing state, utilizing non-volatile logic arrays to store and restore system state quickly, eliminating the need for continuous power and reducing leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If shadow latch is used to retain state information during standby power mode, then data retention is improved, but leakage current is reduced only partially and continuous power is still required
Solution Approach 1:
The patent changes the fundamental parameter of state retention from volatile (requiring continuous power) to non-volatile (retaining state without power). By using ferroelectric RAM (FRAM) with high threshold voltage transistors, the system achieves complete power removal while maintaining data retention, fundamentally changing the power consumption characteristics from continuous to intermittent.
Solution Approach 2:
The patent extracts the state retention function from the volatile logic circuitry and places it in a separate non-volatile storage structure. The shadow latch concept is extended by using FRAM cells that can be selectively coupled to logic arrays, allowing the retention function to operate independently of continuous power supply to the main logic.
2Productivity
If continuous power is supplied to logic arrays, then system performance is maintained, but energy consumption increases
Solution Approach 1:
The patent implements dynamic power management where power supply to logic arrays is switched between active and standby states based on operational requirements. During active operation, full power is supplied for optimal performance. During standby, power is completely removed and state is preserved in non-volatile storage, achieving dramatic energy reduction without permanent performance loss.
Solution Approach 2:
The system employs periodic power cycling where logic arrays are powered on only when computation is needed and powered off during idle periods. The non-volatile storage maintains system state between power cycles, enabling the logic arrays to resume operation quickly without continuous power consumption.
3Loss of energy
If power is completely removed from logic arrays, then energy consumption is minimized, but state information is lost
Solution Approach 1:
The patent implements preliminary state saving before power removal. When transitioning to standby mode, the system first writes the current state of logic arrays to non-volatile FRAM storage, then safely removes power. This preliminary action ensures that when power is restored, the state information is already preserved and can be quickly restored to the logic arrays.
Solution Approach 2:
The non-volatile FRAM storage acts as an intermediary between the volatile logic arrays and the power supply. It receives and holds state information from the logic arrays when power is removed, and can transfer this information back when power is restored, mediating the information preservation across power cycles.
4Loss of energy
If non-volatile logic arrays are used to store and restore system state, then power usage is optimized, but device complexity increases
Solution Approach 1:
The patent merges the volatile logic array functionality with non-volatile storage capabilities into a unified NVL structure. By integrating FRAM cells directly with the logic array architecture, the system achieves non-volatile operation without requiring completely separate storage and retrieval mechanisms, thereby reducing overall device complexity despite the advanced functionality.
Solution Approach 2:
The NVL logic arrays serve multiple functions: they perform logical operations when powered, store state information when unpowered, and can be selectively activated based on operational needs. This multi-functionality consolidates what would traditionally require separate components (volatile logic, non-volatile storage, power management, and state transfer mechanisms) into a single integrated structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables devices to stop and restart without data loss, optimizing power usage and reducing energy consumption, particularly beneficial for energy harvesting applications where intermittent power is available.
Implementation Method 1
non-volatile logic (NVL) within System on Chip (SoC) using ferroelectric random access memory (FRAM)
Data Source
AI summary
A processing device selectively backups only certain data based on a priority or binning structure. In one approach, a non-volatile logic controller stores the machine state by storing in non-volatile logic element arrays a portion of data representing the machine state less than all the data of the machine state. Accordingly, the non-volatile logic controller stores the machine state in the plurality of non-volatile logic element arrays by storing a first set of program data of the machine state according to a first category for backup and restoration and storing a second set of program data of the machine state according to a second category for backup and restoration.