Nonvolatile Logic Array Wakeup Sequencing for Zero-Leakage Sleep
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Solution Overview
Problem
Existing portable electronic devices face challenges in reducing leakage current during standby power mode, requiring continuous power to retain state information, which is inefficient for battery-operated devices and energy harvesting applications.
Innovation Solution
The implementation of non-volatile logic (NVL) in System on Chip (SoC) using ferroelectric random access memory (FRAM) allows for complete removal of power without losing state information, utilizing non-volatile logic arrays to store and restore system state quickly and efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If shadow latch is powered by separate always-on power supply to retain state information, then data retention is improved, but leakage current increases
Solution Approach 1:
The patent extracts the power supply dependency from the shadow latch by implementing non-volatile memory cells that can retain state information without continuous power. The shadow latch is decoupled from the always-on power supply and instead uses non-volatile memory elements that inherently maintain their state without power, thereby eliminating the leakage current associated with keeping the shadow latch powered while preserving data retention capability.
Solution Approach 2:
The patent changes the fundamental parameter of how state information is retained by transitioning from volatile memory (requiring continuous power) to non-volatile memory cells. These non-volatile cells use different physical mechanisms (such as charge trapping, phase change, or resistive switching) to maintain their state without power, fundamentally altering the power consumption characteristics of the shadow latch while maintaining reliability.
2Loss of energy
If multi-threshold CMOS technology is used in shadow latch to reduce leakage current, then energy consumption is improved, but device complexity increases
Solution Approach 1:
The patent uses non-volatile memory cells that replicate the state retention function of the shadow latch without requiring the complex multi-threshold CMOS architecture. By copying the essential function (state retention) using a different technological approach (non-volatile memory elements), the system achieves low leakage current without the complexity of managing multiple transistor threshold voltages.
3Device complexity
If slave latch is configured to operate as retention latch during low power operation, then device complexity is reduced, but system performance deteriorates
Solution Approach 1:
The patent segments the memory system into distinct non-volatile memory cells that are dedicated to state retention, separate from the main volatile memory operations. This segmentation allows the non-volatile cells to handle retention functions independently without interfering with the performance of the main memory system, enabling both low complexity and high performance to coexist.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables zero-leakage sleep mode and instant-on capability, reducing energy consumption and reboot time, making it suitable for energy harvesting applications and handheld devices with limited power resources.
Implementation Method 1
The implementation of non-volatile logic (NVL) in System on Chip (SoC) using ferroelectric random access memory (FRAM) allows for complete removal of power without losing state information
Data Source
AI summary
A processing device includes a plurality of non-volatile logic element array domains having two or more non-volatile logic element arrays to store 2006 a machine state of the processing device stored in a plurality of volatile store elements. Configuration bits are read to direct which non-volatile logic element array domains are enabled first and to direct an order in which the first enabled non-volatile logic element array domains are restored or backed up in response to entering a wakeup or backup mode. Configuration bits can be read to direct an order of and a parallelism of how individual non-volatile logic element arrays in a first enabled non-volatile logic element array domain are restored or backed up. The order of restoration or backing up can be controlled by instructions from non-volatile arrays of the first enabled of the plurality of non-volatile logic element array domains.