NVL Array Wakeup Sequencing for Zero-Leakage Instant-On SoCs
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Solution Overview
Problem
Existing portable electronic devices face challenges in reducing leakage current during standby power mode, requiring continuous power to retain state information, which is inefficient for battery-operated devices and energy harvesting applications.
Innovation Solution
Implementing non-volatile logic (NVL) elements, such as ferroelectric random access memory (FRAM), which allows state retention without power and enables quick system restoration, using a system-on-chip (SoC) design with multiple power domains and NVL arrays to manage state saving and restoration efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If shadow latch is powered by separate always-on power supply to retain data during standby, then data retention is achieved, but leakage current increases
Solution Approach 1:
The patent extracts the power supply function for the shadow latch from the always-on power domain and connects it to the power domain that can be turned off during standby mode. This allows the shadow latch to retain data without requiring continuous power, thereby eliminating leakage current while maintaining data retention capability.
Solution Approach 2:
The shadow latch is designed to function in multiple power modes - it can operate with power during active mode and retain data without power during standby mode. This multi-functionality allows the same circuit to serve both data retention and power-saving purposes, resolving the contradiction between reliability and energy loss.
2Loss of energy
If thick gate oxide transistors and high threshold voltage transistors are used in shadow latch, then leakage current is reduced, but system performance deteriorates
Solution Approach 1:
The patent segments the circuit into two distinct parts: the master latch using standard transistors for high-speed operation during active mode, and the shadow latch using thick gate oxide/high threshold voltage transistors for low-leakage operation during standby mode. This segmentation allows each part to be optimized for its specific function without compromising overall system performance.
Solution Approach 2:
Different transistor types are applied locally to different parts of the latch circuit based on functional requirements. The master latch uses standard transistors for speed, while the shadow latch uses specialized low-leakage transistors for power saving. This local quality differentiation resolves the contradiction between performance and energy loss.
3Reliability
If slave latch is configured to operate as retention latch during low power operation, then data retention is achieved, but some power is still required
Solution Approach 1:
The patent extracts the shadow latch from the power-dependent operation and makes it truly power-independent by connecting it to a power domain that can be completely turned off. This allows the shadow latch to retain data without any power consumption during standby mode, improving upon the slave latch approach that still requires some power.
4Adaptability or versatility
If energy harvester provides very small amount of power, then wireless autonomous operation is enabled, but continuous operation at full power is not sustainable
Solution Approach 1:
The patent implements dynamic power management where the system can switch between active mode (full power operation) and standby mode (zero power consumption) based on available energy from the harvester. This dynamic adaptation allows the system to operate autonomously on harvested energy by entering low-power states when energy is scarce.
Solution Approach 2:
The system employs periodic operation patterns, alternating between active periods (when energy is available) and standby periods (when energy is depleted). This periodic action allows the system to sustain wireless autonomous operation over time by cycling between power states, making efficient use of the limited harvested energy.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables zero-leakage sleep mode and instant-on capability, reducing power consumption and reboot time, making it suitable for energy harvesting applications and handheld devices with limited power resources.
Implementation Method 1
Implementing non-volatile logic (NVL) elements, such as ferroelectric random access memory (FRAM), which allows state retention without power
Data Source
AI summary
Individual first ones of a plurality of non-volatile logic element arrays are designated to restore first in response to entering a wakeup or restoration mode. These non-volatile logic element arrays include instructions for an order in which other non-volatile logic element arrays are to be restored next. So configured, the processing device can be set to have one or more NVL arrays restored first, which arrays are pre-configured to guide further wakeup of the device through directed restoration from particular NVL arrays. Certain NVL arrays can be skipped if the functions stored therein are not needed, and the order of restoration of others can be tailored to a particular wakeup time and power concern through restoration in parallel, serial, or combinations thereof.