NVM Array Partitioning for Static and Dynamic Neural Data

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing non-volatile memory (NVM) arrays face challenges in efficiently managing and storing static and dynamic neural network data, particularly in deep learning applications, where static data requires high retention and write endurance, while dynamic data necessitates high read and write performance, and current solutions often compromise on error correction and verification processes.

Innovation Solution

The implementation of separate NVM access parameters for static and dynamic data within an NVM die, allowing for distinct trim settings that enhance data retention and write endurance for static data, while disabling or reducing error correction and verification for dynamic data to improve read and write performance, thereby optimizing storage and processing efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If separate NVM access parameters are used for static and dynamic data, then data retention and write endurance for static data are improved, but device complexity increases

Engineering Contradiction:
Improvedata retention and write enduranceVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The NVM array is divided into first and second sets of NVM elements, with separate access parameters for static and dynamic data. This segmentation allows independent optimization of retention/endurance for static data and performance for dynamic data without mutual interference.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different trim settings and access parameters are applied to different regions of the NVM array based on data type. Static data regions use parameters optimized for retention and endurance, while dynamic data regions use parameters optimized for read/write performance.

Inventive Principle:
Principle #3Local quality

2Productivity

If error correction and verification processes are reduced for dynamic data, then read and write performance are improved, but reliability deteriorates

Engineering Contradiction:
Improveread and write performanceVSAvoiddata integrity
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

Error correction and verification processes are segmented based on data type. Dynamic data uses reduced error correction/verification for high performance, while static data uses full error correction/verification for high reliability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The error correction and verification parameters are dynamically adjusted based on the data type being accessed. Different trim settings are applied to modify the aggressiveness of error correction and verification processes for different data sets.

Inventive Principle:
Principle #35Parameter changes

3Device complexity

If standard NVM access parameters are used for both static and dynamic data, then device complexity is reduced, but data retention for static data and read/write performance for dynamic data cannot be simultaneously optimized

Engineering Contradiction:
Improvedevice complexityVSAvoidstorage and processing efficiency
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The system segments data into static and dynamic categories with dedicated NVM elements and access parameters for each, enabling simultaneous optimization of retention for static data and performance for dynamic data.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system dynamically selects appropriate access parameters and trim settings based on the data type being accessed, allowing the NVM array to adapt its behavior to optimize for either retention or performance as needed.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS11507843B2Separate storage and control of static and dynamic neural network data within a non-volatile memory array
Publication Date: 2022.11.22 SANDISK TECHNOLOGIES LLC
  • US11507843B2 patent drawing
  • US11507843B2 patent drawing
  • US11507843B2 patent drawing

AI summary

Methods and apparatus are disclosed for managing the storage of static and dynamic neural network data within a non-volatile memory (NVM) die for use with deep neural networks (DNN). Some aspects relate to separate trim sets for separately configuring a static data NVM array for static input data and a dynamic data NVM array for dynamic synaptic weight data. For example, the static data NVM array may be configured via one trim set for data retention, whereas the dynamic data NVM array may be configured via another trim set for write performance. The trim sets may specify different configurations for error correction coding, write verification, and read threshold calibration, as well as different read/write voltage thresholds. In some examples, neural network regularization is provided within a DNN by setting trim parameters to encourage bit flips to avoid overfitting. Some examples relate to managing non-DNN data, such as stochastic gradient data.