Non-Volatile Memory Array Peak Power Management
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Solution Overview
Problem
Non-volatile memory arrays face high peak power demand and noise issues during analog operations, leading to device malfunction and increased power consumption.
Innovation Solution
The memory device incorporates word line and bit line switches that selectively connect and disconnect rows and columns of memory cells to reduce peak current demand by operating only some components at a time, thereby managing peak power and noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If all rows and columns of memory cells are connected to drivers simultaneously during analog operations, then complete array access is achieved, but peak power demand and noise increase causing device malfunction
Solution Approach 1:
The memory array is divided into multiple banks, with each bank having its own set of row and column switches. This segmentation allows selective activation of only certain banks during analog operations, reducing the number of simultaneously active switches and thereby lowering peak power demand and noise while maintaining the ability to access the complete array through sequential or selective bank activation.
2Adaptability or versatility
If all row and column switches are activated simultaneously, then full memory array is accessible, but supply component size and complexity increase
Solution Approach 1:
The switch network is segmented into multiple independent bank groups, each controlled by its own switch set. This allows the system to activate only the necessary subset of banks for any given operation, reducing the complexity of supply components while maintaining full array accessibility through coordinated control of different bank groups.
3Productivity
If analog operations are performed on the entire memory array, then computational capability is maximized, but noise from peak current demand causes device malfunction
Solution Approach 1:
The memory array is partitioned into multiple banks that can be independently activated. During analog operations, only the necessary subset of banks is activated at any given time, distributing the computational workload across time and space. This reduces peak current demand and associated noise, preventing device malfunction while maintaining overall computational capability through coordinated bank operations.
Solution Approach 2:
Analog operations are performed in periodic cycles across different banks rather than simultaneously across the entire array. The controller activates banks in a time-multiplexed manner, allowing each bank to complete its analog computation cycle before the next bank begins. This periodic activation pattern reduces peak noise levels while preserving the total computational throughput of the memory array.
Data Source
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AI summary
A memory device includes rows and columns of memory cells, word lines each connected to a memory cell row, bit lines each connected to a memory cell column, a word line driver connected to the word lines, a bit line driver connected to the bit lines, word line switches each disposed on one of the word lines for selectively connecting one memory cell row to the word line driver, and bit line switches each disposed on one of the bit lines for selectively connecting one memory cell column to the bit line driver. A controller controls the word line switches to connect only some of the rows of memory cells to the word line driver at a first point in time, and controls the bit line switches to connect only some of the columns of memory cells to the bit line driver at a second point in time.