Non-volatile Memory Array Segmentation for Reduced Access Latency
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Solution Overview
Problem
Conventional non-volatile memory (NVM) systems face challenges with access time for read/write operations, particularly due to the length of the main bitline, which introduces latency in operations.
Innovation Solution
The proposed solution involves distributing the components of the read/write interface across multiple memory portions, with sense amplifiers located intermediate these portions, allowing for reduced current flow during read operations and improved access times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the main bitline is made long to accommodate a large memory array, then the memory capacity increases, but the access time increases due to signal propagation delay
Solution Approach 1:
The memory array is divided into multiple memory portions (e.g., four portions), each with its own dedicated sense amplifier. This segmentation allows read operations to be performed on smaller sub-arrays simultaneously, reducing the effective signal propagation distance and access time while maintaining large total memory capacity.
Solution Approach 2:
The patent introduces a new dimension to the bitline architecture by adding intermediate sense amplifiers within the memory array structure. Instead of a single long bitline, multiple shorter bitline segments are created with sense amplifiers positioned at intermediate locations, effectively transforming the single-dimension long bitline into a multi-dimensional structure with reduced propagation delays.
2Device complexity
If the sense amplifier is located at the end of the main bitline, then the structure is simplified, but the access time increases due to longer signal propagation distance
Solution Approach 1:
Rather than placing a single sense amplifier at the end of the main bitline, the patent segments the memory array and places multiple sense amplifiers at intermediate positions between memory portions. This segmentation of the sensing function reduces the distance signals must travel while distributing the sensing capability across multiple locations.
Solution Approach 2:
Intermediate sense amplifiers are introduced as mediator elements within the memory array structure. These sense amplifiers act as intermediate sensing points that reduce the propagation distance from memory cells to sensing elements, effectively mediating between the memory portions and the main bitline.
3Device complexity
If a single main bitline is used for both read and write operations, then the device complexity is reduced, but the access time for read operations increases
Solution Approach 1:
The main bitline is designed with multi-functionality to serve both read and write operations. During write operations, the main bitline carries programming signals to memory cells. During read operations, intermediate sense amplifiers enable local sensing of read currents from memory portions, allowing the same physical bitline structure to perform multiple functions without requiring separate dedicated lines.
Solution Approach 2:
The bitline system is segmented into main bitline segments and local bitline portions, with sense amplifiers positioned at the interfaces. This segmentation allows differentiated operation modes where write operations use the full main bitline while read operations utilize localized sensing paths through intermediate amplifiers, optimizing performance for each operation type.
Data Source
AI summary
A memory device comprises a memory array having memory cells in a set of memory portions and addressable via a pair of row and column values, a set of sense amplifier circuits coupled to and interposed between adjacent memory portions, a control logic circuit configured to provide at least one address signal indicating a pair of row and column values to localize at least one addressed memory cell, and to issue read or write access requests towards the at least one addressed memory cell, a first set of access devices configured to couple an addressed memory cell in a respective memory portion to a respective sense amplifier circuit in response to a read access request, and a second set of access devices configured to couple an addressed memory cell in a respective memory portion to a main programming bitline in response to a write access request.