Non-Volatile Memory Bad Block Management Hardware Circuit
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Solution Overview
Problem
Current non-volatile memory devices face inefficiencies due to the high voltage programming operations in NAND FLASH memories, which can damage cells and lead to reduced capacity over time as software-based bad block management requires significant computational resources and memory space, especially in low-end devices.
Innovation Solution
Implementing a dedicated hardware solution that reserves subsets of memory cells for storing the bad block table, allowing automatic management of defective blocks without reducing user capacity, by using a control circuit to update and store the bad block table in a dedicated RAM, eliminating the need to read the spare area at startup and enabling transparent substitution of failed blocks with redundancy blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If software-based bad block management is used, then bad blocks can be managed and substituted, but computational resources and memory space are significantly consumed
Solution Approach 1:
The patent replaces the software-based bad block management system with a dedicated hardware circuit (BBM circuit). This circuit includes a bad block table storage unit, a comparison unit, and a substitution control unit that work together to automatically manage bad blocks through hardware operations rather than software execution, thereby reducing computational load and memory requirements while maintaining management capability
Solution Approach 2:
The patent introduces a dedicated BBM circuit as an intermediary between the memory array and the controller. This circuit acts as a mediator that handles bad block detection, table management, and substitution operations independently, preventing these operations from consuming the controller's computational resources and general memory space
2Reliability
If the bad block table is stored in general memory space, then it can be updated dynamically, but user capacity is reduced
Solution Approach 1:
The patent segments the memory system into distinct functional areas: a dedicated bad block table storage unit within the BBM circuit, redundancy block areas, and user data areas. The bad block table is stored in a specific reserved region that is separate from user addressable memory, ensuring that the table storage does not encroach on user capacity while still allowing dynamic updates
3Adaptability or versatility
If software algorithms are used to update the bad block table, then flexibility is maintained, but processing time and computational resources increase
Solution Approach 1:
The patent replaces software algorithms with hardware circuit operations. The comparison unit uses hardware logic to compare block addresses against the bad block table, and the substitution control unit uses hardware control signals to redirect accesses. These hardware operations execute in parallel and in constant time, eliminating the sequential processing delays inherent in software algorithms while maintaining the ability to handle various bad block scenarios
Data Source
AI summary
A method of managing fails in a non-volatile memory device including an array of cells grouped in blocks of data storage cells includes defining in the array a first subset of user addressable blocks of cells, and a second subset of redundancy blocks of cells. A third subset of non-user addressable blocks of cells is defined in the array for storing the bad block address table of respective codes in an addressable page of cells of a block of the third subset. Each page of the third subset is associated to a corresponding redundancy block. If during the working life of the memory device a block of cells previously judged good in a test phase becomes failed, each block is marked as bad and the stored table in the random access memory is updated.