Non-volatile Memory Bit Line Discharge Circuit
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Solution Overview
Problem
Conventional non-volatile memory devices experience increased voltage levels on bit and word lines due to leakage currents, leading to faulty operations and reduced reliability during read and write operations.
Innovation Solution
The implementation of a non-volatile memory device with discharge units that selectively discharge non-selected bit lines in a pulse shape before active operations and maintain a level shape during read/write operations, preventing voltage increases by managing reverse currents through diodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional non-volatile memory devices perform read/write operations without discharge units, then the device structure remains simple, but voltage levels on bit and word lines increase due to leakage currents causing faulty operations
Solution Approach 1:
The discharge unit is divided into multiple discharge transistors (first discharge transistor and second discharge transistor) that can independently control discharge paths for different bit lines. This segmentation allows selective discharge of specific bit lines during read/write operations, preventing voltage buildup on inactive lines while maintaining simple operation for active lines.
Solution Approach 2:
The discharge unit acts as an intermediary component between the bit lines and ground, providing a controlled discharge path. The discharge transistors serve as mediators that activate only when needed to remove leakage current accumulation, preventing direct voltage conflicts while maintaining normal read/write functionality.
2Reliability
If discharge units are added to prevent leakage currents, then operation reliability improves, but the number of transistors and control signals increases
Solution Approach 1:
The discharge transistors are merged with the existing bit line selection and read/write control circuitry. The first and second discharge transistors share common control mechanisms with the selection transistors, allowing the discharge function to be integrated into the existing transistor count rather than adding completely separate discharge control transistors for each bit line.
Solution Approach 2:
The discharge transistors serve multiple functions: they discharge leakage current during read/write operations, and can also function as part of the selection mechanism. This multi-functionality reduces the need for separate dedicated discharge transistors for each bit line, thereby limiting the increase in total transistor count.
3Reliability
If discharge units are implemented with multiple discharge transistors, then leakage current control improves, but control signal complexity increases
Solution Approach 1:
The discharge transistors are activated periodically or pulsed during read/write operations rather than continuously. The control signals for the first and second discharge transistors are timed to discharge leakage current at specific moments in the read/write cycle, reducing the need for complex continuous control and allowing simpler signal generation.
Solution Approach 2:
The discharge transistors are activated in advance or at predetermined times during read/write operations to prevent voltage buildup before it causes faults. This preliminary discharge action simplifies control by anticipating the need for discharge rather than reacting to voltage conflicts, reducing control signal complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach substantially reduces leakage currents, enhancing operation reliability and program/read characteristics by maintaining controlled voltage levels on bit and word lines.
Implementation Method 1
a first discharge unit, disposed near the first mat, configured to discharge bit lines other than the selected bit line among the plurality of bit lines according to a plurality of bit line discharge signals
Implementation Method 2
If a voltage and a current are applied to the PCM layer 2, a high temperature is induced in the PCM layer 2, such that an electrical conductive state of the PCM layer 2 changes depending on resistance variation
Implementation Method 3
the PCM layer 2 changes to a crystalline phase or an amorphous phase if heat is applied to the GST, thereby storing data in the memory cell
Implementation Method 4
preventing voltage increases by managing reverse currents through diodes
Data Source
AI summary
A non-volatile memory device includes a plurality of mats, each of which includes a unit cell in an intersection area between each of a plurality of word lines and each of a plurality of bit lines such that a read or write operation of data is achieved in each mat, a column switching unit configured to select any one of bit lines from among the plurality of bit lines according to a column selection signal, and selectively control a connection between the selected bit line and a global bit line, and a discharge unit, in an active mode in which the read or write operation is achieved, configured to discharge the remaining bit lines other than the selected bit line from among the plurality of bit lines in response to a bit line discharge signal.