Non-Volatile Memory Bit Line Grouping for Coupling Reduction
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Solution Overview
Problem
Current non-volatile memory devices face challenges in reducing programming time, data verification time, and coupling effects during data operations, particularly due to capacitive couplings between adjacent bit lines and word lines, which affect the accuracy and efficiency of data storage and retrieval.
Innovation Solution
The method involves dividing bit lines into groups and controlling data writing and verification using varying control and verification voltages, with separate operations for even and odd bit lines to minimize capacitive couplings and optimize programming and verification processes, allowing for simultaneous programming and verification of memory cells connected to adjacent bit lines while reducing the need for repeated precharging and voltage adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is programmed to all memory cells connected to bit lines simultaneously, then programming speed is improved, but capacitive coupling between adjacent bit lines increases causing data accuracy degradation
Solution Approach 1:
The patent divides bit lines into multiple groups (first bit line group and second bit line group) and performs programming operations on different groups at different times. Specifically, memory cells connected to the first bit line group are programmed first, then memory cells connected to the second bit line group are programmed after. This segmentation of the programming process eliminates simultaneous switching of adjacent bit lines, thereby reducing capacitive coupling effects while maintaining acceptable programming speed through staged operation.
2Manufacturing precision
If verification is performed on all bit lines sequentially, then data accuracy is improved, but verification time increases
Solution Approach 1:
The verification process is segmented into multiple stages corresponding to different bit line groups. Verification is performed on the first bit line group, then on the second bit line group, allowing accurate verification of each group separately. This segmented approach achieves thorough verification accuracy while reducing total verification time compared to completely sequential verification of all bit lines one by one, since multiple groups can be verified in parallel stages.
Data Source
AI summary
A method of controlling data includes, with respect to non-volatile memory cells connected to bit lines corresponding to a first bit line group, first controlling data written to the non-volatile memory cells by varying a control voltage, and, with respect to non-volatile memory cells connected to bit lines corresponding to a second bit line group, second controlling data written to the non-volatile memory cells by varying a control voltage. The controlling may include reading or verifying. Before verification, the method may include writing data to the non-volatile memory cells.