Non-Volatile Memory Bit Line Interference Reduction
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Solution Overview
Problem
Bit line interference in non-volatile memory devices, such as flash memory, leads to cell over-programming and incorrect state determination due to parasitic capacitance coupling, which existing methods like topology tuning fail to adequately address without degrading cell reliability and performance.
Innovation Solution
The implementation of an incremental step pulse programming (ISPP) operation scheme that reduces the range of threshold voltages for sets of cells by identifying fast and slow subsets based on detected threshold voltages and applying appropriate bit line biases, thereby minimizing bit line interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If topology tuning methods (air-gap or deeper control gate plug) are used to reduce bit line interference, then bit line interference is reduced, but cell reliability and performance are degraded
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting bit line bias voltages during programming operations. Instead of modifying physical topology, the invention changes electrical parameters (bit line bias voltages) to compensate for interference effects, thereby reducing bit line interference without degrading cell reliability or performance
2Object-affected harmful factors
If topology tuning methods (air-gap or deeper control gate plug) are used to reduce bit line interference, then bit line interference is reduced, but cell performance is degraded
Solution Approach 1:
The patent changes electrical parameters (bit line bias voltages) dynamically during programming to reduce interference effects. This approach maintains cell performance by avoiding physical modifications that would slow down programming operations, instead using voltage adjustments that can be applied rapidly without affecting cell speed or efficiency
3Device complexity
If uniform bit line bias is applied to all cells, then programming process is simplified, but fast and slow cells cannot be optimized individually leading to over-programming
Solution Approach 1:
The patent applies local quality by differentiating bit line bias voltages based on cell characteristics. Fast cells receive one bias voltage while slow cells receive a different bias voltage, allowing each subset to be programmed with optimal parameters. This prevents over-programming of fast cells while ensuring slow cells reach their target threshold voltage, thereby improving measurement precision without excessive complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces bit line interference voltage without compromising cell reliability or performance, ensuring accurate programming and state determination in non-volatile memory devices.
Implementation Method 1
a cell having two states (e.g., 0 and 1) may be placed in a particular state by iteratively applying a programming voltage across the cell
Implementation Method 2
bit line interference has been attributed to a parasitic capacitance coupling effect in which the threshold voltage of one cell is changed by a shifting the threshold voltage of a neighboring cell
Data Source
AI summary
Provided are methods, devices, and/or the like for reducing the bit line interference when programming non-volatile memory. One method comprises providing a non-volatile memory device comprising a set of cells, each cell associated with a bit line; shooting a programming voltage across each cell; detecting a threshold voltage for each cell; identifying a fast subset of the set of cells and a slow subset of the set of cells based at least in part on the detected threshold voltage for each cell; and shooting the programming voltage until the threshold voltage for each cell is greater than a verify voltage. For each shot a fast bit line bias is applied to the bit line associated each cell of the fast subset and a slow bit line bias is applied to the bit line associated with each cell of the slow subset.