Non-volatile Memory Bit Line Voltage Control
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Solution Overview
Problem
Non-volatile memory devices experience irregular voltage drops during programming, affecting data transfer efficiency and increasing execution time due to the structure of bit lines and the application of variable voltages.
Innovation Solution
The non-volatile memory device incorporates a selecting unit with NMOS transistors and a pre-charge mechanism that applies variable voltages to even and odd bit lines, pre-charging them to half the voltage level to prevent voltage drops and reduce execution time, ensuring stable data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If variable voltage is applied to bit lines during programming, then data transfer capability is improved, but voltage level becomes unstable and decreases irregularly
Solution Approach 1:
The patent applies preliminary action by pre-charging bit lines to a first voltage level before programming operations. The selecting unit pre-establishes voltage levels on bit lines in advance, so when programming occurs, the voltage is already stabilized and ready for immediate data transfer without subsequent drops or instability.
Solution Approach 2:
The selecting unit acts as an intermediary between the voltage supply and the bit lines. It controls and regulates the voltage applied to each bit line, preventing direct voltage drops from affecting the bit lines. The detecting node also serves as an intermediary to monitor voltage levels and trigger appropriate responses.
2Ease of operation
If voltage is applied to selecting unit of bit line, then control over bit line voltage is improved, but execution time increases due to voltage decreases during program
Solution Approach 1:
The selecting unit performs preliminary actions by pre-charging bit lines to the required voltage level before the actual programming operation begins. This eliminates the need for voltage adjustments during programming, thereby reducing execution time while maintaining ease of control.
Solution Approach 2:
The detecting node provides feedback by monitoring the voltage level of bit lines and generating discharge signals when voltage drops are detected. This feedback mechanism allows the selecting unit to maintain voltage control without excessive execution time, as corrections are triggered only when necessary.
3Reliability
If variable voltage is applied to even and odd bit lines, then data transfer stability is improved, but device complexity increases due to additional control mechanisms
Solution Approach 1:
The patent divides the bit line control into separate even and odd bit lines, each with dedicated selecting units and control mechanisms. This segmentation allows independent control of each bit line, improving data transfer stability by preventing cross-interference and voltage drops from affecting all lines simultaneously.
Solution Approach 2:
The selecting unit is designed with multi-functionality, serving both to charge bit lines to specific voltage levels and to control the transfer of data during programming. The detecting node also performs multiple functions: monitoring voltage levels and triggering discharge operations. This reduces overall device complexity by consolidating functions.
Data Source
AI summary
A non-volatile memory device comprises an even bit line and an odd bit line contacting to a memory cell array. A register unit includes a first register and a second register for temporarily storing data. A detecting node detects a voltage level of the specific bit line or the specific register which is connected to the bit lines and the registers. A selecting unit of the bit line includes a first variable voltage input terminal and a second variable voltage input terminal. The first variable voltage input terminal applies a first variable voltage of a specific voltage level to the even bit line in response to an even discharge signal. The second variable voltage input terminal applies a second variable voltage of a specific voltage level to the odd bit line in response to an odd discharge signal.