Image Recognition Accelerator Using NVM Bit Segmentation
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Solution Overview
Problem
Existing image recognition technologies on mobile devices face high system power consumption due to the need for low write currents to reduce error rates in SRAM, leading to increased CPU complexity and static power consumption, limiting battery lifespan.
Innovation Solution
An image recognition accelerator that employs a dimensionality-reduction processing module, non-volatile memory, and an image matching module to store image data using different currents for low-order and high-order bits, optimizing power consumption while maintaining recognition accuracy by adjusting parameters such as the dimensionality-reduction parameter, width parameter, and current based on success rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the write current is lowered to reduce system power consumption during image data analysis, then power consumption is reduced, but the error rate of data stored in SRAM increases
Solution Approach 1:
The patent segments image data into high-order bits and low-order bits, storing them in different memory regions (SRAM and NVM respectively). This segmentation allows different error tolerance strategies for different parts of the data, enabling lower write currents in NVM for power savings while maintaining overall data reliability through the structure of segmented storage and subsequent reconstruction.
Solution Approach 2:
The patent changes the physical state and storage parameters by transitioning from traditional volatile SRAM storage to non-volatile memory (NVM) with different electrical characteristics. By adjusting write current parameters and utilizing NVM's ability to retain data without power, the system achieves lower power consumption while maintaining acceptable error rates through the combined storage architecture and data reconstruction processes.
2Measurement precision
If convex optimization processing is used to recover stored image data, then data accuracy is improved, but CPU computing complexity increases
Solution Approach 1:
The patent performs preliminary dimensionality reduction on image data before storage, transforming the data into a compressed representation that reduces the computational burden of subsequent recovery operations. This preliminary processing simplifies the reconstruction task, allowing accurate data recovery with reduced CPU complexity compared to full-resolution optimization.
Solution Approach 2:
The patent stores a compressed or transformed copy of the image data (dimensionality-reduced representation) in NVM rather than the full original data. This copied representation requires less computational resources to process and recover, while still enabling accurate reconstruction of the original image data through the inverse transformation, thus reducing CPU complexity.
3Reliability
If SRAM is kept in power-on state to protect stored data, then data reliability is maintained, but static power consumption increases
Solution Approach 1:
The patent utilizes non-volatile memory (NVM) which inherently retains data without requiring continuous power, replacing the need to keep SRAM in a powered state. NVM acts as a disposable-like storage medium that maintains data integrity without static power consumption, allowing the system to power down completely while preserving stored image data.
Solution Approach 2:
The patent extracts the data retention function from volatile SRAM and places it in non-volatile memory (NVM). By separating the storage function from the processing function and utilizing NVM's inherent data retention capability, the system eliminates the need to maintain SRAM in a powered state, thereby removing static power consumption while preserving data reliability.
4Productivity
If dimensionality reduction is applied to image data, then processing speed is improved, but information loss may occur
Solution Approach 1:
The patent performs dimensionality reduction as a preliminary step before storage, transforming image data into a compressed representation that retains essential features. This pre-processing enables faster subsequent processing and recovery operations while the structured storage and reconstruction methods preserve sufficient information for accurate image recognition, balancing speed and information retention.
Data Source
AI summary
An image recognition accelerator, a terminal device, and an image recognition method are provided. The image recognition accelerator includes a dimensionality-reduction processing module, an NVM, and an image matching module. The dimensionality-reduction processing module first reduces a dimensionality of first image data. The NVM writes, into a first storage area of the NVM according to a specified first current I, ω low-order bits of each numeric value of the first image data on which dimensionality reduction has been performed, and writes, into a second storage area of the NVM according to a specified second current, (N−ω) high-order bits of each numeric value of the first image data on which dimensionality reduction has been performed. The image matching module determines whether an image library stored in the NVM includes image data matching the first image data on which dimensionality reduction has been performed.