NVM Bitcell with FN Tunneling for Fast Erasure
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Solution Overview
Problem
Current nonvolatile memory (NVM) devices face challenges in achieving high bitcell density and cost-effectiveness, with existing solutions like FLASH requiring additional processing steps and EEPROM having large bitcell sizes, limiting their application and manufacturing efficiency.
Innovation Solution
A nonvolatile memory bitcell design incorporating a transistor, capacitor, and Fowler-Nordheim tunneling device linked by a single floating gate, which allows for simultaneous programming and erasure without a separate selection device, utilizing standard CMOS processes to reduce manufacturing costs and increase bitcell density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If FLASH memory is used to achieve small bitcell size, then bitcell area is reduced, but additional processing steps are required which increases manufacturing cost
Solution Approach 1:
The memory device is segmented into distinct functional regions: a first region containing FLASH memory bitcells with tunneling devices for fast programming, and a second region containing EEPROM-like bitcells for storage. This segmentation allows each region to be optimized independently, enabling small bitcell area in the FLASH region while using standard CMOS processes in the EEPROM region to avoid additional manufacturing costs.
Solution Approach 2:
Different memory technologies are applied to different regions based on local requirements. The FLASH region uses tunneling devices and specific doping profiles optimized for fast programming, while the EEPROM region uses standard complementary doped regions optimized for nonvolatile storage. This local quality approach allows each region to achieve its optimal performance characteristics without compromising the other.
2Ease of manufacture
If EEPROM is used to achieve compatibility with standard CMOS processes, then manufacturing cost is reduced, but bitcell size becomes large limiting memory capacity
Solution Approach 1:
The patent merges FLASH memory technology and EEPROM technology into a single hybrid device. The FLASH region provides high-density storage with small bitcell area using tunneling devices, while the EEPROM region provides nonvolatile storage with standard CMOS compatibility. Both regions share common structure elements and can be fabricated using standard CMOS processes, achieving high capacity while maintaining manufacturing compatibility.
3Adaptability or versatility
If separate selection devices are used for programming and reading, then device functionality is improved, but bitcell complexity and area increase
Solution Approach 1:
The tunneling device serves multiple functions: it acts as the selection device for programming operations, as the charge storage mechanism for data retention, and as part of the read operation through its capacitive coupling. This multi-functionality eliminates the need for separate selection transistors, reducing bitcell complexity and area while maintaining full programming and reading functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves higher bitcell density and lower manufacturing costs by eliminating the need for additional processing steps, enabling efficient and cost-effective production of NVM devices with improved write cycle endurance and faster testing capabilities.
Implementation Method 1
A nonvolatile memory bitcell design incorporating a transistor, capacitor, and Fowler-Nordheim tunneling device linked by a single floating gate
Data Source
AI summary
A nonvolatile memory (“NVM”) bitcell includes a capacitor, a transistor, and a tunneling device. The capacitor, transistor, and tunneling device are each electrically coupled to different active regions and metal contacts. The three devices are coupled by a floating gate that traverses the three active regions. The tunneling device is used to program and erase the device, allowing for faster page erasure, and thus allows for rapid testing and verification of functionality. The transistor is used to read the logical state of the floating gate. The capacitor and floating gate are capacitively coupled together, removing the need for a separate selection device to perform read, write, and/or erase operations.