NVM Bitcell Replacement Control Gate and Floating Gate Design
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Nonvolatile memory bitcells using high-K gate oxides face significant memory effects and trap-assisted leakage issues due to high trap density, leading to data retention problems and increased power consumption.
Innovation Solution
A nonvolatile memory bitcell design featuring two oxide barriers, with a silicon dioxide bottom barrier and a higher dielectric constant top barrier, separates a logic floating gate from both a high-K barrier and a substrate, and incorporates a replacement metal control gate to mitigate memory effects and reduce size and power requirements, constructed using CMOS logic processes of 22 nanometers and below.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If high-K materials are used as gate oxides to reduce device size and power consumption, then device size and power requirements decrease, but trap density increases causing memory effects and data retention problems
Solution Approach 1:
The gate oxide is segmented into multiple layers: a thin high-K dielectric layer for low power consumption and a thicker low-K dielectric layer (SiO2) for high reliability and data retention. This segmentation allows each layer to perform its optimal function - the high-K layer reduces power while the low-K layer prevents trap-assisted leakage.
Solution Approach 2:
The patent uses a composite gate oxide structure combining high-K dielectric material (for low power) with low-K dielectric material SiO2 (for high reliability). This composite approach allows the system to benefit from both materials - the high-K material reduces power consumption while the low-K material prevents trap-assisted leakage and memory effects.
2Volume of moving object
If high-K materials are used as gate oxides to reduce device size, then device dimensions decrease, but trap density increases causing memory effects
Solution Approach 1:
The gate oxide is segmented into multiple layers: a thin high-K dielectric layer for small device size and a thicker low-K dielectric layer (SiO2) for high reliability and memory effect resistance. This segmentation allows each layer to perform its optimal function - the high-K layer enables device miniaturization while the low-K layer prevents trap-assisted leakage.
Solution Approach 2:
The patent uses a composite gate oxide structure combining high-K dielectric material (for small device size) with low-K dielectric material SiO2 (for high reliability). This composite approach allows the system to benefit from both materials - the high-K material enables device scaling while the low-K material prevents trap-assisted leakage and memory effects.
3Reliability
If traditional SiO2 gate oxides are used to ensure low trap density, then data retention is improved, but device size and power consumption increase
Solution Approach 1:
The gate oxide is segmented into multiple layers: a thin high-K dielectric layer for small device size and a thicker low-K dielectric layer (SiO2) for high reliability and data retention. This segmentation allows each layer to perform its optimal function - the high-K layer enables device miniaturization while the low-K layer ensures data retention.
Solution Approach 2:
The patent uses a composite gate oxide structure combining high-K dielectric material (for small device size) with low-K dielectric material SiO2 (for high reliability). This composite approach allows the system to benefit from both materials - the high-K material enables device scaling while the low-K material ensures data retention with low trap density.
4Reliability
If over-programming is used to compensate for memory effects, then data retention is improved, but barrier dielectric wear and inability to perform future write operations increase
Solution Approach 1:
The patent extracts and removes the source of the problem - the trap-rich high-K dielectric layer is separated from direct contact with the floating gate by a trap-free low-K dielectric layer. This eliminates the need for over-programming compensation, allowing normal programming operations to achieve desired data retention without causing barrier wear or preventing future write operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively prevents memory effects and trap-assisted leakage, enabling reliable long-term data storage with reduced power and size requirements, while allowing for the use in various memory types such as embedded flash, MRAM, and ferroelectric RAM without significant heat impact on logic devices.
Implementation Method 1
The floating gate is referred to as 'floating' because the gate is electrically isolated from the surroundings by an oxide or dielectric
Implementation Method 2
The amount of charge residing on a floating gate determines whether the bitcell is storing a logical '1' or a logical '0'
Implementation Method 3
Electrons are capable of moving from one trap to another if the traps are in close proximity. This trap hopping is called trap assisted leakage
Data Source
Figure 1a~1b
Figure 2a~2b
Figure 3
AI summary
Embodiments relate to a nonvolatile memory ("NVM") bitcell with a replacement metal control gate and an additional floating gate. The bitcell may be created using a standard complementary metal-oxide-semiconductor manufacturing processes ("CMOS processes") without any additional process steps, thereby reducing the cost and time associated with fabricating a semiconductor device incorporating the NVM bitcell.