NVM Memory Boot Versioning for Fast Zero Initialization

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Solution Overview

Problem

The increasing memory capacity and demand in computing systems using Non-Volatile Memory (NVM) technologies lead to prolonged boot times due to the need for costly write transactions during memory zeroing, especially with slower write bandwidths in technologies like Phase Change Memory, which can take several minutes and significantly impact system performance.

Innovation Solution

Implementing a 'fast zero' technique that uses a Boot Version Number for each portion of NVM memory, updating it on every boot, and returning zeros on read operations if there's a mismatch, thereby avoiding actual zeroing operations and improving performance by leveraging metadata to emulate zero states without writing to NVM.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional memory zeroing is performed during boot, then memory is properly initialized, but boot time is significantly prolonged

Engineering Contradiction:
Improvememory initialization accuracyVSAvoidboot time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent creates a copy of the zero state metadata in the form of a version number that indicates whether memory has been zeroed. Instead of physically writing zeros to memory during boot, the system uses a version number copy to represent the zeroed state, allowing fast verification without time-consuming write operations.

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The patent performs memory zeroing metadata updates in advance during write operations. When memory is written to, the version number is updated to reflect that the memory has been modified from its zeroed state. This preliminary tracking eliminates the need for time-consuming zeroing operations during boot.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If NVM write operations are performed during boot, then memory is initialized, but power consumption increases

Engineering Contradiction:
Improvememory initializationVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent replaces energy-intensive physical write operations with lightweight metadata version number updates. The version number serves as a copy that tracks the zeroed state without requiring actual memory write transactions, dramatically reducing power consumption during boot.

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The patent substitutes the mechanical/electrical process of writing zeros to NVM with a logical operation on a version number. This replacement eliminates the high-power write transactions required by NVM technology while achieving the same initialization objective through low-power metadata manipulation.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Quantity of substance

If NVM write bandwidth is limited, then memory capacity can be large, but memory zeroing speed decreases

Engineering Contradiction:
Improvememory capacityVSAvoidmemory zeroing speed
Core Design Contradiction:
Quantity of substanceVSProductivity

Solution Approach 1:

The patent uses a version number copy to represent the zeroed state of large memory capacities. This approach allows the system to support very large NVM capacities without being constrained by limited write bandwidth, since updating a version number is much faster than writing zeros across the entire memory space.

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The patent performs only the minimal necessary action of updating a version number rather than performing excessive write operations across the entire memory space. This partial action approach maintains support for large memory capacities while achieving fast initialization by acting only on the metadata rather than the full memory space.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentEP3161622B1Accelerating boot time zeroing of memory based on non-volatile memory (NVM) technology
Publication Date: 2022.05.25 INTEL CORP
  • EP3161622B1 patent drawingFigure 1
  • EP3161622B1 patent drawingFigure 2
  • EP3161622B1 patent drawingFigure 3

AI summary

Methods and apparatus to accelerate boot time zeroing of memory based on Non-Volatile Memory (NVM) technology are described. In an embodiment, a storage device stores a boot version number corresponding to a portion of a non-volatile memory. A memory controller logic causes an update of the stored boot version number in response to each subsequent boot event. The memory controller logic returns a zero in response to a read operation directed at the portion of the non-volatile memory and a mismatch between the stored boot version number and a current boot version number. Other embodiments are also disclosed and claimed.