Non-Volatile Memory Buffer Management for Write Speed

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Solution Overview

Problem

Flash memory devices, such as SD/eMMC cards, face significant degradation in write speed and increased P/E cycling due to the need to rewrite entire erase blocks for random access data sectors, leading to excessive delays and limited cycle lifetimes.

Innovation Solution

A method of managing non-volatile memory by partitioning the memory space into subsets, merging data sectors from different data blocks into a sequential portion before the buffer becomes full, and maintaining metadata for efficient data location and allocation, which reduces the frequency of full buffer conditions and subsequent merge operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If the controller manages memory at the erase block level to simplify memory management, then device complexity is reduced, but write speed degrades significantly due to frequent full block rewrites

Engineering Contradiction:
Improvememory management complexityVSAvoidwrite speed
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent divides the erase block into multiple segments (data blocks) and introduces a buffer structure. Data is written to the buffer first, and only when the buffer is full does the system perform a merge operation to write to the erase block. This segmentation allows partial data updates without rewriting the entire block, thus improving write speed while maintaining manageable complexity through structured organization.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a buffer as an intermediary structure between the data input and the erase block. This buffer acts as a mediator that accumulates data until it reaches a threshold (full buffer condition), at which point a merge operation is triggered. This intermediary layer decouples the frequent small writes from the expensive full block writes, resolving the contradiction between simplicity and write performance.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of operation

If random access data sectors are written to flash memory, then data accessibility is improved, but P/E cycling increases excessively leading to reduced device lifespan

Engineering Contradiction:
Improvedata accessibilityVSAvoiddevice lifespan
Core Design Contradiction:
Ease of operationVSDuration of action of stationary object

Solution Approach 1:

The patent performs preliminary actions by maintaining a buffer that accumulates data before triggering merge operations. Instead of immediately writing each random access sector to the erase block, the system preliminarily stores data in the buffer and batches writes together. This preliminary buffering reduces the frequency of P/E cycles, thereby extending device lifespan while preserving random access capability through the buffer management structure.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements periodic merge operations that occur when the buffer becomes full, rather than after every single write operation. This periodic action pattern converts frequent random writes into less frequent batch writes, reducing P/E cycling frequency and extending device lifespan while maintaining data accessibility through the buffer-mediated access model.

Inventive Principle:
Principle #19Periodic action

3Quantity of substance

If frequent merge operations are performed to maintain buffer efficiency, then memory utilization is improved, but response time increases due to operational delays

Engineering Contradiction:
Improvememory utilizationVSAvoidresponse time
Core Design Contradiction:
Quantity of substanceVSLoss of time

Solution Approach 1:

The patent applies partial action by performing merge operations only when the buffer reaches a specific condition (full buffer), rather than after every write or at fixed intervals. This threshold-based trigger ensures that merge operations occur with optimal frequency - not too frequently to waste time, but not too infrequently to waste space. The partial action principle balances memory utilization and response time by acting only when necessary.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS9396106B2Advanced management of a non-volatile memory
Publication Date: 2016.07.19 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD
  • US9396106B2 patent drawing
  • US9396106B2 patent drawing
  • US9396106B2 patent drawing

AI summary

A method of managing a non-volatile memory device, the method comprising: receiving data sectors; writing each data sector into a data block that is allocated to a memory space subset that is associated with the data sector; wherein the data block belongs to a buffer of the non-volatile memory device; maintaining a management data structure that comprises location metadata about a location of each data sector in the buffer; and merging, if a criterion is fulfilled and before the buffer becomes full, data sectors stored at different data blocks and belong to a same set of logical memory blocks into a sequential portion of the non-volatile memory device, wherein the sequential portion differs from the buffer.