Non-volatile Memory Cache Latch Voltage Scaling
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Solution Overview
Problem
The integration of non-volatile memory devices with decreasing power source voltage leads to a slow discharge rate, hindering high-speed operation due to the time it takes for the voltage difference between input/output lines to reach a predetermined level.
Innovation Solution
A non-volatile memory device design that utilizes a higher second power source voltage for the cache latches, switches, and pre-charger, allowing for increased pre-charge levels and operation voltages, which accelerates the discharge process by pre-charging input/output lines with the second power source voltage and using transistors to drive data nodes and bar nodes effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a lower power source voltage is used for integration, then device integration is improved, but discharge rate deteriorates
Solution Approach 1:
The patent applies different voltage parameters to different functional blocks: a first power source voltage (e.g., 1.8V) is supplied to the sense amplifier, while a second power source voltage higher than the first (e.g., 3.6V) is supplied to the cache latch, switch, and pre-charger. This parameter differentiation allows the pre-charger to charge I/O lines to a higher voltage level, creating a larger voltage swing during discharge operations and thereby improving discharge rate without compromising integration.
2Speed
If pre-charge level is increased, then discharge rate is improved, but power consumption increases
Solution Approach 1:
The patent applies high voltage locally only to components that benefit from it (pre-charger, cache latch, and switch) while keeping the sense amplifier at a lower voltage. This localized application of high voltage optimizes discharge rate for the critical path without unnecessarily increasing power consumption across the entire read path.
Data Source
AI summary
A non-volatile memory device includes: a plurality of cache latches; a pair of input/output lines; a plurality of switches, each couples a corresponding cache latch to the pair of the input/output lines, when the corresponding cache latch is selected among the plurality of cache latches; a pre-charger suitable for pre-charging the pair of the input/output lines; and a sense-amplifier suitable for sensing and amplifying the data of the pair of the input/output lines, wherein the sense-amplifier operates with a first power source voltage, and the plurality of the cache latches, the plurality of the switches, and the pre-charger operate with a second power source voltage having a voltage level that is higher than the voltage level of the first power source voltage.