Single Gate NVM Capacitor Doping Design for Coupling Efficiency
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Solution Overview
Problem
In deep sub-micron integrated circuit technology, single floating gate non-volatile memory devices face challenges due to capacitors with low coupling efficiency and large circuit area, leading to large memory cell size and low cell-density.
Innovation Solution
The design incorporates a metal-insulating-semiconductor (MIS) sandwich structure capacitor with a second doped well acting as an electrode, isolated from the data-storing structure, allowing operation in enhancement mode with increased coupling efficiency and capacitance by reducing the effective distance between electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a capacitor is used in a single floating gate NVM device with conventional structure, then data storage function is achieved, but coupling efficiency is low and circuit area is large
Solution Approach 1:
The patent changes the doping type parameter of the well from conventional (opposite to transistor) to same type as transistor, enabling the capacitor to operate in enhancement mode. This parameter change increases coupling efficiency without requiring larger capacitor area, directly resolving the technical contradiction between reliability and area.
2Reliability
If capacitor area is increased to improve coupling efficiency, then coupling efficiency increases, but memory cell size increases
Solution Approach 1:
By changing the doping type parameter to enable enhancement mode operation, the patent achieves higher coupling efficiency with the same capacitor area. This allows memory cell size to remain small while improving coupling efficiency, resolving the contradiction between reliability and moving object area.
3Ease of manufacture
If conventional capacitor structure is used, then manufacturing is simple, but coupling efficiency is low leading to low cell-density
Solution Approach 1:
The patent modifies the doping type parameter while maintaining the same capacitor structure and manufacturing process. This parameter change improves coupling efficiency and cell-density without complicating manufacturing, resolving the contradiction between ease of manufacture and productivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances coupling efficiency and capacitance, enabling smaller memory cell size and higher cell-density without increasing capacitor area, thus addressing the limitations of existing single floating gate NVM devices.
Implementation Method 1
a second doped well of a first-type dopant and formed in the semiconductor substrate
Implementation Method 2
metal-insulating-semiconductor (MIS) sandwich structure capacitor
Data Source
AI summary
The NVM device includes a semiconductor substrate having a first region and a second region. The NVM device includes a data-storing structure formed in the first region and designed operable to retain charges. The NVM device includes a capacitor formed in the second region and coupled with the data-storing structure for data operations. The data-storing structure includes a first doped well of a first-type in the semiconductor substrate. The data-storing structure includes a first gate dielectric feature on the first doped well. The data-storing structure includes a first gate electrode disposed on the first gate dielectric feature and configured to be floating. The capacitor includes a second doped well of the first-type. The capacitor includes a second gate dielectric feature on the second doped well. The capacitor also includes a second gate electrode disposed on the second gate dielectric feature and connected to the first gate electrode.