NVM Cell Design Eliminates Sense Amplifiers via Direct Voltage Read
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Solution Overview
Problem
Existing non-volatile memory (NVM) cells require large area due to the need for sense amplifiers and latching circuits to read data, which increases size and complexity.
Innovation Solution
The NVM cell design includes an NMOS control transistor, a PMOS erase transistor, and inverter transistors with a simplified circuitry that uses two supply voltage levels to directly read output voltage, eliminating the need for sense amplifiers and latching circuits by translating data into rail-to-rail output voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If sense amplifiers and latching circuits are used to read data from NVM cells, then data reading capability is improved, but device area and complexity increase significantly
Solution Approach 1:
The patent extracts and eliminates the sense amplifier and latching circuit from the NVM cell structure. By using a differential cell configuration where one cell is programmed and the other serves as a reference, the reading function is achieved through direct current comparison without requiring separate sense amplification and latching stages, thus reducing device complexity while maintaining data reading capability
Solution Approach 2:
The patent merges the reading function into the basic cell structure by using a differential pair configuration. The programmed cell and reference cell form a current mirror that directly provides the read output, combining the storage and read functions into a unified simple structure that eliminates the need for separate sense amplifiers and latching circuits
2Ease of operation
If sense amplifiers and latching circuits are added to NVM cells, then data reading is enabled, but manufacturing cost and area increase
Solution Approach 1:
The patent removes the sense amplifier and latching circuit components from the cell structure. The differential configuration allows direct reading through current comparison between programmed and reference cells, eliminating the need for additional area-consuming circuits and reducing overall cell area
Solution Approach 2:
The reference cell serves multiple functions: it acts as a stored reference value for comparison and simultaneously provides the bias current for the differential pair. This multi-functionality eliminates the need for separate reference circuits and sense amplifiers, reducing the total area required per cell
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces the size and complexity of the NVM cell array while maintaining low current consumption and simple programming sequences, allowing direct reading of output voltage without additional circuitry, thus enhancing efficiency and reducing area requirements.
Implementation Method 1
the all-PMOS 4-transistor NVM cell disclosed therein relies on reverse Fowler-Nordheim tunneling for programming. That is, when the potential difference between the floating gate electrode of the programming transistor of the all-PMOS NVM cell and the drain, source and bulk region electrodes of the programming transistor exceeds a tunneling threshold voltage, electrons tunnel from the drain and source electrodes to the floating gate
Data Source
AI summary
An NVM cell design enables direct reading of cell output voltage to determine data stored in the cell, while providing low current consumption and a simple program sequence that utilizes reverse Fowler-Nordheim tunneling.