5-Transistor NVM Cell Floating Drain Source Regions
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Solution Overview
Problem
The existing 4-transistor all-PMOS non-volatile memory (NVM) cell design results in a limited voltage difference between programmed and non-programmed cells due to trapped charge on non-programmed cells, leading to 'disturbed' cells with reduced noise margin and data retention.
Innovation Solution
A 5-transistor NVM cell design is introduced, replacing the PMOS control transistor with an NMOS control transistor and adding NMOS pass gate transistors, allowing the drain and source regions of non-programmed cells to float during programming, thereby increasing the voltage difference between programmed and non-programmed cells without disturbing their initial state.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a 4-transistor all-PMOS NVM cell design is used with reverse Fowler-Nordheim tunneling programming, then low current consumption and simple programming sequence are achieved, but the voltage difference between programmed and non-programmed cells is limited due to trapped charge on non-programmed cells
Solution Approach 1:
The patent divides the transistor functions into separate NMOS and PMOS devices. Specifically, it uses NMOS for control and data transistors while using PMOS only for the erase transistor. This segmentation allows the control and data transistors to have their drain and source regions floating during programming, preventing charge trapping and increasing the voltage difference between programmed and non-programmed cells.
Solution Approach 2:
The patent inverts the traditional all-PMOS configuration by using NMOS transistors for the control and data functions. This inversion changes the operating characteristics, allowing the drain and source regions of non-programmed cells to float at higher potentials during programming, thereby increasing the voltage difference between programmed and non-programmed cells without disturbing the initial state of non-programmed cells.
2Reliability
If the drain and source regions of non-programmed cells are set to a fixed inhibiting voltage during programming, then the programming sequence is simplified, but the floating gate voltage of non-programmed cells is disturbed, reducing noise margin and data retention
Solution Approach 1:
The patent makes the drain and source regions of the control and data transistors dynamic rather than fixed. During programming, these regions float at a potential determined by the control voltage and erase voltage, rather than being held at a fixed inhibiting voltage. This dynamic behavior prevents charge trapping and maintains the initial state of non-programmed cells, improving noise margin and data retention.
Solution Approach 2:
The patent introduces the control voltage and erase voltage as intermediary potentials that mediate the behavior of the transistor regions. Instead of directly setting drain and source regions to a fixed inhibiting voltage, the system uses the control and erase voltages to indirectly control the potential of these regions, allowing them to float appropriately during programming and preventing disturbance to non-programmed cells.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The 5-transistor NVM cell achieves a larger voltage difference between programmed and non-programmed cells, enhancing noise margin and data retention while maintaining the advantages of reverse Fowler-Nordheim tunneling programming.
Implementation Method 1
the all-PMOS 4-transistor NVM cell disclosed therein relies on reverse Fowler-Nordheim tunneling for programming. That is, when the potential difference between the floating gate electrode of the programming transistor of an all-PMOS NVM cell and the drain, source and bulk electrodes of the programming transistor exceeds a tunneling threshold voltage, electrons tunnel from the drain and source electrodes to the floating gate, making the floating gate negatively charged.
Data Source
AI summary
A non-volatile memory (NVM) cell comprises an NMOS control transistor having commonly-connected source, drain and bulk region electrodes and a gate electrode connected to a storage node; a PMOS erase transistor having commonly-connected source, drain and bulk region electrodes and a gate electrode connected to the storage node; an NMOS data transistor having source, drain and bulk region electrodes and a gate electrode connected to the storage node, the bulk region electrode being connected to a common bulk node; the first NMOS pass gate transistor having a source electrode connected to the drain electrode of the NMOS data transistor, a drain electrode, a bulk region electrode connected to the common bulk node, and a gate electrode; and a second NMOS pass gate transistor having a drain electrode connected to the source electrode of the NMOS data transistor, a source electrode, a bulk region electrode connected to the common bulk node, and a gate electrode.