NVM Cell Array Readout Using Cells as Load Elements
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Solution Overview
Problem
Conventional Non-Volatile Memory (NVM) readout methods require additional transistors or resistors as loading elements, which occupy silicon area and increase manufacturing costs due to complex metal line routing in tight pitch spacings.
Innovation Solution
Using NVM cells or series of NVM cells as loading elements in the NVM array, operating in the linear mode to function as resistors, thereby eliminating the need for extra loading elements and simplifying the readout circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional loading elements (transistors or resistors) are used in NVM readout circuits, then reliable information retrieval is achieved, but silicon area increases and manufacturing complexity increases
Solution Approach 1:
NVM cells are made to serve dual functions: storing information and acting as loading elements during readout operations. By configuring NVM cells in series strings and applying appropriate voltages to word lines and bit lines, the same NVM cell array performs both memory storage and the loading function traditionally requiring separate transistors or resistors, thereby eliminating additional silicon area requirements
Solution Approach 2:
The patent merges the storage function and loading function into a single integrated structure using NVM cells. Instead of having separate loading elements connected to each NVM cell, the NVM cells themselves are combined to form series strings that provide the necessary loading characteristics during readout, reducing overall circuit complexity and area
2Ease of operation
If conventional loading elements (transistors or resistors) are used in NVM readout circuits, then information can be read out, but device complexity and manufacturing cost increase
Solution Approach 1:
NVM cells perform multiple functions including storage and loading operations. By applying different voltage levels to word lines (e.g., V0 for selected cells, V1 for unselected cells) and controlling bit line voltages, the same NVM cell array provides both information storage and the loading function needed for readout, eliminating the need for separate loading circuitry
Solution Approach 2:
The patent uses parameter changes in voltage application to control the operation mode of NVM cells. By varying word line voltages (V0, V1, V2 levels) and bit line voltages, the NVM cells transition between different operational states (storage mode, readout mode, loading mode), enabling the same hardware to perform different functions without additional circuitry
3Area of stationary object
If NVM cells are used as loading elements, then silicon area is saved and manufacturing is simplified, but additional voltage control mechanisms are required
Solution Approach 1:
The NVM cell array serves dual purposes as both storage elements and loading elements. By configuring cells in series strings and applying appropriate voltage levels to word lines and bit lines, the same NVM infrastructure provides both storage capacity and the loading function traditionally requiring separate components, thereby saving silicon area without adding significant control complexity
Solution Approach 2:
The patent employs dynamic voltage control where word line voltages and bit line voltages are adjusted during different operational phases (write, read, erase). The voltage levels (V0, V1, V2) are dynamically changed to control which NVM cells are selected and to put them in the appropriate operational mode, enabling flexible control of the multi-functional NVM array
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach saves silicon area, reduces manufacturing costs, and simplifies metal line routing, leading to smaller chip sizes and lower manufacturing costs while maintaining effective information retrieval from NVM cells.
Implementation Method 1
when a MOSFET is running in the linear region, where the magnitude of the applied gate voltage relative to the source voltage over the device threshold voltage is much higher than that of the drain voltage relative to the source voltage, an inversion layer on the surface of the MOSFET channel is formed to electrically link the source electrode and drain electrode. The inversion layer is filled with mobile charge carriers such as electrons for an N-type MOSFET and holes for a P-type MOSFET, respectively. Under this linear condition, the MOSFET behaves like a resistor. The current flowing through the MOSFET is proportional to the applied voltage bias between the source electrode and the drain electrode.
Data Source
AI summary
A Non-Volatile Memory (NVM) cell in an NVM array is read out using other NVM cells in the array as a load element. Conventional load elements such as MOS transistors or resistors used to vary the bitline potential for the NVM cell readout in conventional NVM arrays are replaced with NVM cell(s) in the array. The omission of the extra MOS transistors or resistors for the load elements not only saves silicon area but also simplifies the bitline sensing circuitry design in the NVM array.