Non-Volatile Memory Cell With Select Transistor
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Solution Overview
Problem
Conventional single gate non-volatile memory cells have inefficiencies in programming and erasing speed, small read current margins, and reliability issues due to the storage of data in a single store transistor, making it difficult to distinguish between program and erase states after multiple cycles.
Innovation Solution
A non-volatile memory cell design utilizing three transistors, including two store transistors with coupled gates acting as a floating gate and a select transistor, where the bit is stored or erased by controlling the bit line and select gate line, with specific voltage applications to improve operation speed and distinguishability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is stored in a single store transistor, then the device complexity is reduced, but the programming speed and erasing speed cannot be improved
Solution Approach 1:
The patent divides the single store transistor into two separate store transistors (first store transistor and second store transistor) with opposite conductive types. This segmentation allows independent control of programming and erasing operations, thereby improving programming speed and erasing speed while maintaining reasonable device complexity through systematic architecture design.
Solution Approach 2:
The patent combines the gates of the first store transistor and second store transistor to form a coupled gate structure that functions as a floating gate. This merging enables the two transistors to work cooperatively, achieving faster programming and erasing speeds while sharing common control signals, thus balancing performance improvement with device complexity management.
2Measurement precision
If a single store transistor is used, then the device structure is simplified, but the read current margin becomes small making it difficult to distinguish program and erase states
Solution Approach 1:
By segmenting the storage function across two transistors with opposite conductive types, the patent creates distinct current paths for program and erase states. This segmentation significantly increases the read current margin, allowing clear distinction between stored states even after multiple programming/erasing cycles, while the coupled gate structure maintains architectural simplicity.
Solution Approach 2:
The patent applies different conductive types to different transistors (first store transistor with first conductive type, second store transistor with second conductive type opposite to the first). This local differentiation of electrical properties enables enhanced read current margins through complementary device characteristics, improving state distinguishability without requiring complex external circuitry.
3Reliability
If finite programming/erasing operation cycles are applied to a single gate cell, then the operation is completed, but the difference of read currents becomes hard to distinguish reducing reliability
Solution Approach 1:
The patent segments the storage function into two transistors that can be independently controlled during programming and erasing operations. This segmentation prevents cumulative degradation of read current distinction, maintaining reliable state differentiation even after finite operation cycles by allowing selective refresh and independent transistor optimization.
Solution Approach 2:
The patent implements dynamic control through the select transistor that can selectively activate either the first store transistor or second store transistor based on operation requirements. This dynamic switching capability allows the system to adapt to different operation cycles, maintaining reliable read current differentiation by periodically refreshing the appropriate transistor state and preventing cumulative degradation.
Data Source
AI summary
A non-volatile memory cell and methods for programming, erasing and reading thereof are provided. A non-volatile memory cell includes a substrate having a first conductive type. A first transistor, a second transistor and a select transistor having a second conductive type are disposed in the substrate, wherein a first gate of the first transistor is coupled to a second gate of the second transistor. A source region of the first transistor is coupled to a bit line. A drain region of the second transistor and a gate of the select transistor are coupled to a select gate line. A drain region of the first transistor is coupled to a source region of the select transistor. A drain region of the select transistor is coupled to a select line.