Non-Volatile Memory Cell With Stacked Floating Gates
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Solution Overview
Problem
Current non-volatile memory (NVM) cells face issues of large cell size, low bit density, slow write speeds, and reliance on LDMOS devices, which limit their efficiency and functionality.
Innovation Solution
The implementation of a NVM cell design featuring a transistor with a wordline gate structure and floating gate structures laterally positioned between diffusion regions, coupled with a capacitor having control gate structures and additional floating gate structures, allowing for faster write and erase operations without requiring LDMOS devices, and enabling high bit density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional NVM cell designs are used, then fast write and erase speeds can be achieved, but the cell size becomes large and bit density decreases
Solution Approach 1:
The patent transitions from traditional planar NVM cell layouts to a three-dimensional stacked architecture where multiple memory cells are vertically stacked above a common bitline. This vertical stacking enables multiple cells to share the same lateral footprint, dramatically increasing bit density while maintaining fast write and erase speeds through the preserved transistor-capacitor coupling geometry.
2Ease of manufacture
If simpler integration processes are used, then manufacturing complexity decreases, but write speeds become slow
Solution Approach 1:
The patent employs a universal standard logic CMOS fabrication process that can manufacture both the transistor and capacitor structures using the same process steps. The transistor shares common diffusion regions and gate structures with the capacitor, allowing a single integrated circuit process to create both memory cell components without requiring separate LDMOS fabrication lines, thereby maintaining fast write speeds while simplifying manufacturing.
3Speed
If LDMOS devices are used, then fast write operations are achieved, but device complexity increases
Solution Approach 1:
The patent extracts and eliminates the LDMOS device requirement from the NVM cell structure by designing a capacitor-coupled cell that operates with standard logic CMOS transistors. The invention removes the need for complex laterally-diffused metal-oxide-semiconductor devices by using a different operational mechanism based on capacitive coupling between the transistor and capacitor, thereby reducing device complexity while maintaining fast write and erase capabilities.
4Device complexity
If OTP only functionality is provided, then device simplicity is maintained, but erase functionality is lost
Solution Approach 1:
The patent implements dynamic erase functionality by enabling the capacitor to be discharged through the transistor channel during erase operations. The cell can be programmed by injecting charge into the capacitor and erased by controlling the transistor to discharge the capacitor, providing both write and erase capabilities through dynamic control of the transistor-capacitor coupling rather than static OTP functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design results in significantly smaller memory cell size, faster write and erase operations, and higher bit density, while minimizing gate oxide stress for improved reliability and eliminating the need for LDMOS devices.
Implementation Method 1
providing a capacitor having first, second, and third control gate structures over the substrate, a third floating gate structure between the first and second control gate structures
Implementation Method 2
positively biasing the wordline gate structure and one of the first and second diffusion regions; coupling another one of the first and second diffusion regions to a ground rail; and positively biasing the first, second, and third control gate structures
Implementation Method 3
negatively biasing the wordline gate structure, the first, second, and third control gate structures, and the third and fourth diffusion regions; positively biasing one of the first and second diffusion regions
Data Source
AI summary
A non-volatile memory cell with high bit density is disclosed. Embodiments include: providing a transistor having a wordline gate structure over a substrate, first and second floating gate structures proximate opposite sides of the wordline gate structure, and first and second diffusion regions in the substrate, wherein the wordline gate structure, the first floating gate structure, and the second floating gate structure are laterally between the first and second diffusion regions; and providing a capacitor having first, second, and third control gate structures over the substrate, a third floating gate structure between the first and second control gate structures, a fourth floating gate structure between the second and third control gate structures, and third and fourth diffusion regions in the substrate, wherein the first, second, and third control gate structures are laterally between the third and fourth diffusion regions.