Non-Volatile Memory Cell Band-to-Band Tunneling Injection
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Solution Overview
Problem
The existing non-volatile memory technologies face challenges in accurately controlling the logical states of memory cells due to difficulties in managing high energy electron injection and tunneling processes, especially as transistor dimensions decrease, leading to insufficient or excessive charge levels on floating gates.
Innovation Solution
The implementation of a non-volatile memory cell circuit that utilizes both impact ionization and band-to-band tunneling currents to maintain the desired charge level on the floating gate, with a second transistor designed to inject electrons through band-to-band tunneling even when the first transistor is not sufficiently 'on', ensuring consistent logical state transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single transistor is used for electron injection into the floating gate, then the device structure remains simple, but the electron flow becomes insufficient when the floating gate voltage is too high
Solution Approach 1:
The patent combines two transistors (first transistor for impact ionization and second transistor for band-to-band tunneling) into a single memory cell structure. Both transistors work simultaneously to inject electrons into the floating gate, merging their injection currents to overcome the limitation of single-transistor insufficiency while maintaining a relatively compact integrated structure
Solution Approach 2:
The second transistor is designed to perform a universal electron injection function that complements the first transistor. It provides band-to-band tunneling current that supplements the impact ionization current, ensuring that electron injection can occur effectively across a wider range of floating gate voltage conditions
2Reliability
If the floating gate voltage is increased to maintain logical state, then the storage capacity is improved, but the electron injection from the first transistor becomes insufficient
Solution Approach 1:
The patent changes the injection mechanism parameter by introducing band-to-band tunneling (second transistor) to supplement impact ionization (first transistor). This parameter change in the injection mechanism allows effective electron injection even when floating gate voltage is high, as the tunneling mechanism is less sensitive to the reduced electric field conditions
3Area of moving object
If transistor dimensions are reduced to increase density, then the memory capacity is improved, but the control of electron injection and tunneling becomes less accurate
Solution Approach 1:
The dual-transistor structure provides an inherent feedback mechanism where the second transistor compensates for injection deficiencies. When the first transistor's injection is insufficient due to dimensional scaling effects, the second transistor's tunneling current automatically supplements it, creating a self-regulating system that maintains charge level control accuracy despite reduced transistor dimensions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures sufficient electron flow into the floating gate over a wider range of operating regions, effectively compensating for the limitations of the first transistor and maintaining accurate logical state transitions, even when the floating gate voltage is too high.
Implementation Method 1
high energy electrons are added to the floating gate 101 from transistor Q1. Here, the WELL/SOURCE voltage 102 is set to a voltage that causes a substantial VSD voltage drop from the source to the drain of the Q1 transistor. These high energy holes collide with the semiconductor substrate lattice from which transistor Q1 is constructed. The collisions with the lattice create high energy electrons that have enough energy to surmount transistor Q1's gate dielectric energy barrier and travel to the floating gate 101
Implementation Method 2
A band-to-band tunneling current flows between valence and conduction bands of the second transistor to create a second injection current that flows through the second gate dielectric to establish the first amount of electrical charge on the gate electrode
Implementation Method 3
a large positive voltage is placed on the ERASE node 103 so as to create a strong electric field that runs from the semiconductor substrate portion of transistor Q2 to the floating gate 101. This large positive voltage causes the energy band structure of the gate dielectric of transistor Q2 to resemble a sharp spike which promotes the tunneling of electrons through the energy barrier that resides between the floating gate 101 and the semiconductor substrate portion of transistor Q2
Data Source
AI summary
Electronic circuitry is described having a first transistor having a first gate dielectric located between an electrically floating gate and a semiconductor substrate. The first injection current flows through the first gate dielectric to establish a first amount of electrical charge on the gate electrode. The electronic circuitry also includes a second transistor having a second gate dielectric located between the gate electrode and the semiconductor substrate. A band-to-band tunneling current flows between valence and conduction bands of the second transistor to create a second injection current that flows through the second gate dielectric to establish the first amount of electrical charge on the gate electrode. Non volatile memory cell circuits having the above described circuitry are also described.