Non-volatile Memory Cell Voltage Sharing Transistor
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Solution Overview
Problem
Conventional non-volatile memory technologies are limited by high operating voltages, which restrict their utility in low-voltage platforms and result in large circuit size and high power consumption, even when boost schemes are used to elevate voltages.
Innovation Solution
A non-volatile memory cell structure is designed with a voltage sharing transistor that blocks high voltage levels, allowing transistors to operate at lower voltages, reducing circuit size and power consumption by using core transistors instead of I/O transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional I/O MOSFETs are used in non-volatile memory, then the memory can operate at higher voltages (around 1.5V), but the circuit size and power consumption become large
Solution Approach 1:
The patent segments the voltage handling function by introducing a dedicated voltage sharing transistor (T2) that specifically manages high voltage levels from the source line, while allowing other transistors (T3, T4) to operate at lower core voltages. This functional segmentation enables different parts of the circuit to operate at optimized voltage levels, reducing overall circuit size while maintaining reliability.
Solution Approach 2:
The voltage sharing transistor T2 acts as an intermediary element between the high-voltage source line and the rest of the memory cell circuitry. It mediates the voltage levels, blocking high voltage from reaching transistors that don't need it, thereby enabling lower voltage operation in those components and reducing their size.
2Reliability
If boost schemes are used to elevate operating voltage, then the memory can operate at higher voltages (1.2V), but the circuit size and power consumption remain large
Solution Approach 1:
The patent segments the voltage boosting function to only where necessary - specifically at the source line interface through transistor T2. Other parts of the circuit (transistors T3, T4) operate at lower core voltages without requiring boost schemes, thereby reducing overall power consumption while maintaining adequate operating voltage where needed.
Solution Approach 2:
The patent applies different voltage quality requirements to different parts of the circuit. The source line interface (T2) handles high voltage locally where needed for programming operations, while the core memory cell transistors (T3, T4) operate at lower voltages, optimizing power consumption and reducing the need for extensive voltage boosting infrastructure.
3Reliability
If I/O transistors are used instead of core transistors, then the memory can handle higher voltages, but the circuit size increases
Solution Approach 1:
The patent segments the transistor types by function: T2 is implemented as an I/O transistor specifically for handling high voltage from the source line, while T3 and T4 are implemented as smaller core transistors that operate at lower voltages. This segmentation allows each transistor to be optimally sized for its specific function, minimizing overall circuit area.
Solution Approach 2:
Transistor T2 serves as an intermediary that handles the high voltage interface requirements, allowing T3 and T4 to be smaller core transistors that don't need to handle high voltages directly. This intermediary arrangement enables the use of smaller transistors in the majority of the circuit while maintaining voltage handling capability where required.
Data Source
AI summary
The invention provides a non-volatile memory cell structure and non-volatile memory apparatus using the same. The non-volatile memory cell structure includes a substrate, first to three wells and first to three transistors. The first to three wells are disposed in the substrate, and the first to three transistors are respectively forming on the first to three wells. The first to third transistors are coupled in series. Wherein, a control end of the first transistor is floated, a control end of the second transistor receives a bias voltage, and a control end of the third transistor is coupled to a word line signal. Moreover, the third well and the second cell are in same type, and the type of the first well is complementary to a type of the third well.