Split-Gate NVM Cell Channel Width Optimization
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Solution Overview
Problem
Non-volatile memory cells in integrated circuits face premature failure due to limited program/erase cycles, causing increased threshold voltage and reduced read margin, especially in data NVMs that are programmed and erased more frequently.
Innovation Solution
Implementing a split-gate non-volatile memory cell configuration with a larger channel width in data NVMs compared to code NVMs, enhancing channel transconductance by at least 25%, which mitigates the effects of edge nanocrystals and allows for higher program/erase cycles without reducing read margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If data NVM uses the same cell configuration as code NVM, then manufacturing is simplified, but the data NVM suffers from premature failure due to limited program/erase cycles
Solution Approach 1:
The patent applies local quality by configuring data NVM cells with a larger channel width specifically in regions subjected to frequent program/erase cycles, while code NVM cells maintain a standard channel width. This localized structural modification enhances the data NVM's ability to withstand repeated cycling without affecting the overall manufacturing process complexity, as both cell types share the same basic split-gate architecture and can be fabricated using similar process steps with adjusted dimensional parameters for the data region.
2Reliability
If the channel width is increased in data NVMs, then transconductance and endurance are improved, but the cell area increases
Solution Approach 1:
The invention implements local quality by increasing the channel width only in the data NVM portion of the integrated circuit, while maintaining the standard channel width in the code NVM portion. This selective dimensional modification targets the specific region that requires enhanced transconductance and cycle endurance, thereby improving reliability without proportionally increasing the total memory cell area across the entire device.
Solution Approach 2:
The patent applies parameter changes by modifying the channel width dimension specifically for data NVM cells to achieve higher transconductance values (at least 25% improvement as stated in the summary). This parameter adjustment directly addresses the need for better signal detection capability and increased program/erase cycle endurance in data storage regions, while the code NVM region maintains its original dimensional parameters.
Data Source
AI summary
An integrated circuit including data and code non-volatile memory configuration is provided. The integrated circuit comprises a first non-volatile memory array for storing code and a second non-volatile memory array for storing data. The first non-volatile memory array comprises a plurality of first non-volatile memory cells, the first non-volatile memory cells each having a first channel width. The second non-volatile memory array comprises a plurality of second non-volatile memory cells, the second non-volatile memory cells each having a second channel width. The second channel width of the second non-volatile memory cells is larger than the first channel width of the first non-volatile memory cells. This allows the data non-volatile memory cells to have a higher transconductance than the code non-volatile memory cells.