Non-volatile Memory Circuit Segmentation for Leakage Reduction
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Solution Overview
Problem
Existing memory circuits face challenges in reducing power consumption and improving reliability due to high voltage stresses on non-selected non-volatile memory (NVM) devices in adjacent banks during program and read operations.
Innovation Solution
A dual path, hierarchical arrangement is implemented to distribute high voltage levels during program and read operations, ensuring that non-selected NVM devices receive either a low voltage or ground voltage level, thereby reducing current leakage and high voltage stresses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high voltage is applied to all NVM devices during program and read operations, then programming and reading operations can be performed, but power consumption increases and reliability decreases due to current leakage in non-selected devices
Solution Approach 1:
The memory system is divided into multiple banks, and the high voltage activation is segmented to affect only the selected bank during program and read operations. Non-selected banks remain at low voltage, preventing current leakage while allowing operations in the selected bank. This segmentation resolves the contradiction by spatially separating the high voltage application to only where needed.
Solution Approach 2:
High voltage activation is applied locally only to the selected bank rather than uniformly to all banks. The activation signal is routed selectively to enable high voltage stress only in the target bank, while other banks maintain low voltage states. This local quality approach reduces overall power consumption and improves reliability by eliminating unnecessary high voltage exposure in non-selected devices.
2Manufacturing precision
If high voltage is applied during program operations, then the dielectric material can be sustainably altered to program the anti-fuse bit, but high voltage stresses and current leakage occur in non-selected NVM devices
Solution Approach 1:
The high voltage programming operation is segmented to affect only the selected bank containing the target anti-fuse bit. The activation signal is routed selectively to the chosen bank, ensuring that high voltage stress is applied only where programming is intended. This prevents harmful high voltage effects on anti-fuse bits in non-selected banks while maintaining programming precision in the target device.
Solution Approach 2:
High voltage stress is applied locally only to the selected bank during programming operations. The system uses selective activation routing to concentrate the high voltage effect precisely where needed for anti-fuse bit modification, while non-selected banks remain at low voltage. This local quality approach ensures programming precision without exposing other devices to harmful high voltage stresses.
3Adaptability or versatility
If conventional memory circuit architecture is used, then device functionality is achieved, but area requirements are large due to HV drivers needed in each bank
Solution Approach 1:
The high voltage activation signal generation is consolidated into a universal resource shared across all banks. Instead of each bank having its own dedicated HV driver, a single HV driver in the control circuit generates activation signals that are routed selectively to different banks as needed. This multi-functional approach maintains full memory functionality while dramatically reducing the total area required for HV drivers.
Solution Approach 2:
Multiple high voltage driver functions are merged into a single shared HV driver located in the control circuit. The unified driver generates activation signals that can be routed to any bank, combining what would otherwise be separate driver circuits in each bank. This merging reduces redundant circuitry and minimizes the overall area occupied by HV driver components while preserving complete memory operational capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power consumption and improves the reliability of NVM devices by minimizing current leakage and high voltage stresses, while also reducing area requirements in HV drivers.
Implementation Method 1
a programming electric field is applied across the dielectric material layer to sustainably alter (e.g., break down) the dielectric material, thus decreasing the resistance of the dielectric material layer
Data Source
AI summary
A memory circuit includes first and second NVM devices and a driver circuit including first and second power switches and first and second drivers. The first and second power switches generate first and second power signals, the first and second drivers output first and second activation signals to the first and second NVM devices responsive to the first and second power signals, respectively, and the driver circuit is configured to output a third activation signal having a voltage less than that of the first activation signal to the first NVM device and to output a fourth activation signal having a voltage less than that of the second activation signal to the second NVM device. The first activation signal and the third activation signal are based on a first enable signal, and the second activation signal and the fourth activation signal are based on a second enable signal.