Non-volatile Memory Command Window for DDR Interface
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Solution Overview
Problem
Existing non-volatile DDR memory devices require different communication buses and operation protocols compared to DDR SDRAMs, leading to resource-intensive solutions that are not optimized for mobile terminals with limited resources, where fast data storage and retrieval are necessary.
Innovation Solution
A non-volatile memory device with a memory matrix and a command window that includes volatile buffer registers, allowing for efficient data transfer and operation management using a common protocol similar to DDR SDRAMs, enabling faster write operations by utilizing a flag bit for data transfer to a command window, thus reducing the complexity and time required for writing data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If non-volatile DDR memory devices use different communication buses and operation protocols compared to DDR SDRAMs, then the non-volatile memory can be optimized for its specific write operations, but the resource usage increases and the device complexity increases
Solution Approach 1:
The patent implements a universal command interface that allows the non-volatile memory device to accept and process both standard SDRAM commands and non-volatile memory-specific commands through the same communication bus and protocol. The command window acts as an intermediary that translates and routes commands appropriately, enabling a single bus to serve multiple memory types with different operational requirements.
Solution Approach 2:
The command window serves as an intermediary layer between the communication bus and the memory array. It receives commands from the bus, interprets them, and executes appropriate operations including data transfer to buffer registers, program operations to the memory array, and verification. This intermediary structure allows complex non-volatile memory operations to be managed through a simplified standard interface.
2Reliability
If non-volatile memory uses traditional write operations with multiple voltage pulses and verification steps, then the data can be reliably programmed, but the write time increases significantly compared to volatile memory
Solution Approach 1:
The patent implements a command window with buffer registers that receive and stage data before it is programmed to the memory array. This preliminary action allows data to be prepared and verified in advance, and enables overlapping of data transfer and program operations. The buffer registers hold data temporarily, allowing the memory controller to initiate program operations without waiting for complete data transfer, thus reducing overall write time while maintaining programming reliability.
3Productivity
If non-volatile DDR memory uses the same interfaces and communication buses as DDR SDRAMs, then resource usage is optimized for mobile terminals, but the operation protocol complexity increases to accommodate both memory types
Solution Approach 1:
The patent designs the non-volatile memory device to implement a universal command interface that is compatible with standard SDRAM protocols. The command window can interpret both SDRAM commands (for volatile operation mode) and non-volatile memory commands (for permanent storage mode), allowing a single communication bus to serve both memory types without requiring separate interfaces or protocols.
Solution Approach 2:
The command window dynamically adapts its operation based on the type of command received. It can switch between different operational modes including standard SDRAM data transfer modes and non-volatile memory program/verify modes. This dynamic behavior allows the same hardware interface to handle multiple protocol requirements without increasing physical complexity.
Data Source
AI summary
A non volatile memory device includes a first buffer register configured to receive and store the data to be stored into the memory device provided via a memory bus. A command window is activatable for interposing itself for access to a memory matrix between the first buffer element and the memory matrix. The command window includes a second buffer element that stores data stored in or to be stored into a group of memory elements. A first data transfer means executes a first transfer of the data stored in the second buffer register into the first buffer register during a first phase of a data write operation started by the reception of a first command. A second data transfer means receives the data provided by the memory bus and modifies, based on the received data, the data stored in the first buffer register during a second phase of the data write operation started by the reception of a second command. The first transfer means execute a second transfer of the modified data stored in the first buffer register into the second buffer register during a third phase of the data write operation. The second transfer is executed in response to the reception of a signal received by the memory bus together with the second command.