Non-Volatile Memory Concurrent Partition Access

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Current memory architectures allow access to only a single partition of memory at a time, limiting data throughput and efficiency during memory access operations.

Innovation Solution

The implementation of a memory system that enables multithread, concurrent access to multiple partitions using control circuitry and timing rules to manage memory access commands, allowing simultaneous processing of multiple memory access threads across different partitions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If memory is divided into partitions to enable concurrent access, then data throughput is improved, but device complexity increases due to multiple local controllers and timing management

Engineering Contradiction:
Improvedata throughputVSAvoidcontrol circuitry complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The memory array is divided into multiple partitions, each with its own local controller, enabling independent concurrent access to different memory regions. This segmentation allows multiple memory access operations to proceed simultaneously without interference, directly improving data throughput.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Local controllers act as intermediaries between the external interface and individual memory partitions. Each local controller manages timing and control signals for its specific partition, simplifying the overall control architecture by distributing control functions rather than requiring a single complex controller.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If single-partition access is used, then device complexity is reduced, but data throughput is limited

Engineering Contradiction:
Improvedata throughputVSAvoidmemory architecture complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The memory system is segmented into multiple partitions that can be accessed concurrently. This segmentation enables parallel memory operations, significantly increasing data throughput compared to single-partition access while maintaining manageable complexity through modular design.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a new dimension of concurrency by enabling multiple memory access operations to proceed simultaneously in different time windows. This temporal multiplexing across partitions creates a multidimensional access pattern that increases throughput without requiring proportional increases in architectural complexity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Productivity

If concurrent multi-partition access is enabled, then productivity increases, but reliability may be affected due to timing conflicts and control challenges

Engineering Contradiction:
Improveconcurrent access efficiencyVSAvoiddata integrity
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The controller performs preliminary actions by establishing proper timing sequences and control signal sequences before concurrent memory access operations begin. By pre-calculating and managing the timing relationships between different partition accesses, the system ensures data integrity is maintained during concurrent operations.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system incorporates feedback mechanisms where local controllers monitor the status of memory access operations and adjust timing signals accordingly. This feedback loop ensures that timing conflicts are detected and resolved, maintaining data integrity while enabling concurrent access across multiple partitions.

Inventive Principle:
Principle #23Feedback

Data Source

PatentEP3403184B1Apparatuses and methods for concurrently accessing multiple partitions of a non-volatile memory
Publication Date: 2023.11.08 MICRON TECHNOLOGY INC
  • EP3403184B1 patent drawingFigure 1
  • EP3403184B1 patent drawingFigure 2
  • EP3403184B1 patent drawingFigure 3

AI summary

Apparatuses and methods for performing multithread, concurrent access of different partition of a memory are disclosed herein. An example apparatus may include a non-volatile memory array comprising a plurality of partitions, each may include a respective plurality of memory cells. The apparatus may further include a plurality of local controllers that are each configured to independently and concurrently access a respective one of the plurality of partitions to execute a respective memory access command responsive to receiving the respective memory access command. The example apparatus may further include a controller configured to receive the plurality of memory access commands and determine a respective target partition for each of the plurality of memory access commands. The controller may be further configured to provide each of the plurality of memory access commands to a local controller of the plurality of local controllers associated with the respective target partition.