Non-volatile Memory Concurrent Sub-block Programming
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Solution Overview
Problem
Existing semiconductor memory systems face challenges in programming data efficiently, leading to prolonged wait times for host devices due to the sequential nature of memory cell programming.
Innovation Solution
The proposed solution involves a non-volatile memory system with multiple planes and sub-blocks, where memory cells are arranged in multiple planes to enable parallel programming, and divided into sub-blocks for independent erasure, reading, and programming. This system uses offset regions based on the diameter of vertical columns to modify the standard programming voltage signal, allowing concurrent programming of memory cells across different word lines in various sub-blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory cells are programmed sequentially using standard voltage signals, then programming simplicity is maintained, but programming speed and throughput deteriorate
Solution Approach 1:
The memory block is divided into multiple sub-blocks (first sub-block and second sub-block) that can be programmed independently and concurrently. Each sub-block has its own set of word lines and memory cells, allowing parallel programming operations without interfering with each other. This segmentation enables multiple programming operations to occur simultaneously, improving throughput while maintaining manageable control complexity through modular organization.
Solution Approach 2:
The patent introduces a new dimension of parallelism by utilizing multiple sub-blocks that can be programmed concurrently. Instead of programming memory cells in a single sequential dimension, the system adds a parallel dimension by applying different voltage signals (first programming voltage signal and second programming voltage signal) to different sub-blocks at the same time, thereby increasing overall programming speed.
2Productivity
If multiple memory cells are programmed in parallel across different word lines, then programming throughput improves, but voltage signal interference and control complexity worsen
Solution Approach 1:
By dividing the memory block into separate sub-blocks with distinct word line sets, the patent isolates voltage signals applied during programming. When programming the first sub-block, voltage signals are applied only to word lines within that sub-block, preventing interference with memory cells in the second sub-block. This physical and electrical segmentation eliminates cross-talk and interference while enabling parallel programming operations.
Solution Approach 2:
The patent uses sub-block isolation structures and selective voltage signal routing as intermediaries to prevent direct interference between parallel programming operations. These intermediaries allow multiple programming operations to occur simultaneously by ensuring that voltage signals applied to one sub-block do not affect memory cells in other sub-blocks, thereby enabling high-throughput parallel programming without signal interference.
Data Source
AI summary
A non-volatile memory system includes a control circuit connected to non-volatile memory cells. The control circuit is configured to concurrently program memory cells connected to different word lines that are in different sub-blocks of different blocks in different planes of a die.