Configurable Registers for Flexible NVM Address Decoding
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Solution Overview
Problem
Conventional multicore devices face high implementation and verification costs due to the need to hardcode numerous memory map addressing schemes for software-over-the-air updates and device emulation across various configuration modes, making it expensive and inflexible to accommodate design changes.
Innovation Solution
The use of configurable registers in non-volatile memory integrated circuit devices to decode address ranges, allowing for flexible support of memory device emulation and bank swapping, reducing the need for hardcoding each combination of address ranges in hardware.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory map addressing schemes are hardcode enumerated into device hardware, then device reliability for SOTA updates and emulation is ensured, but implementation cost and verification complexity increase significantly
Solution Approach 1:
The patent implements dynamic address space configuration by replacing static hardcode enumeration with programmable address space descriptors that can be configured at runtime. The device allows memory map addressing schemes to be dynamically programmed through registers, enabling flexible adaptation to different configuration modes (linear, SOTA-A, SOTA-B) without requiring hardware redesign or extensive verification of each combination.
Solution Approach 2:
The patent changes the parameter representation of address spaces by using programmable base addresses, sizes, and access permissions stored in descriptors rather than fixed hardware-encoded values. This allows the same hardware to support multiple addressing schemes by simply changing the descriptor parameters, reducing implementation complexity while maintaining reliability through programmable control.
2Adaptability or versatility
If multiple configuration modes are supported with hardcode enumeration, then comprehensive device emulation capability is achieved, but verification cost and implementation expense increase
Solution Approach 1:
The patent implements a universal address space management mechanism that can handle multiple configuration modes (linear, SOTA-A, SOTA-B) and device emulation scenarios through a single programmable framework. The address space descriptors and translation mechanisms are designed to be mode-agnostic, allowing the same hardware structure to serve multiple functions without requiring separate hardcode enumeration for each mode, thereby improving ease of manufacture while maintaining comprehensive adaptability.
3Measurement precision
If hardcode enumeration is used for each address range combination, then precise address decoding is ensured, but design change flexibility is reduced
Solution Approach 1:
The patent replaces static hardcode address decoding with dynamic address space descriptors that can be programmed at runtime. The descriptors contain base addresses, sizes, and access permissions that can be modified to support different device configurations and emulation modes, maintaining precise address decoding while enabling flexible design changes without hardware modification.
Data Source
AI summary
A non-volatile memory (NVM) integrated circuit device includes a processing device and an NVM array of memory cells partitioned into a first physical region and a second physical region. The NVM integrated circuit device also includes a plurality of routing circuits, a first decoder associated with a first routing circuit, and a second decoder associated with a second routing circuit. The NVM integrated circuit device also includes a first programmable register coupled to the plurality of routing circuits, wherein the first programmable register is to store a first multi-bit value, the first multi-bit value programmed by the processing device to configure a first address range associated with the first decoder. The NVM integrated circuit device also includes a second programmable register coupled to the plurality of routing circuits, wherein the second programmable register is to store a second multi-bit value, the second multi-bit value programmed by the processing device to configure a second address range associated with the second decoder.