NVM Controller Block Aperture for Persistent Memory Addressing
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Solution Overview
Problem
Conventional computer systems experience latency in block write/read operations due to I/O processing performed by block storage device controllers over PCIe buses, which limits the effective use of non-volatile memory devices.
Innovation Solution
A non-volatile memory (NVM) device controller with a block window (aperture) that allows direct memory access and address translation, enabling the host processor to access persistent data without physical addressing constraints, thereby reducing latency and maximizing NVM device capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If I/O processing is performed by block storage device controller over PCIe bus, then data access is enabled, but latency increases
Solution Approach 1:
The patent extracts the I/O processing function from the block storage device controller and relocates it to the host processor. This allows the controller to operate more efficiently as a simpler device while the host processor handles the complex I/O operations, thereby reducing latency without concentrating all complexity in one device.
Solution Approach 2:
The patent introduces a memory-mapped I/O interface as an intermediary between the host processor and block storage device controller. This intermediary enables direct memory access and simplifies the communication path, reducing latency while distributing the processing complexity between the host processor and the controller.
2Adaptability or versatility
If physical addressing is used for NVM access, then direct memory access is enabled, but address space is constrained by host processor limits
Solution Approach 1:
The patent introduces an address translation mechanism as an intermediary layer between the host processor's physical addressing system and the NVM device's address space. This translation layer allows the system to access the full capacity of large NVM devices while maintaining compatibility with the host processor's addressing limitations.
Solution Approach 2:
The patent changes the addressing parameter from direct physical addresses to translated logical addresses. This allows the system to overcome the host processor's physical addressing limits by using a different addressing scheme that can accommodate larger address spaces required by high-capacity NVM devices.
3Speed
If PCIe bus is used for communication, then device connectivity is achieved, but processing speed is limited
Solution Approach 1:
The patent extracts the complex PCIe bus interface requirements from the block storage device controller and relocates them to the host processor. This allows the controller to operate at higher speeds with simpler interfacing, while the host processor handles the complex bus protocol operations.
Solution Approach 2:
The patent introduces a memory-mapped I/O interface as an intermediary that simplifies the communication path between the host processor and NVM device. This intermediary enables faster data transfer by using memory bus protocols instead of traditional PCIe I/O protocols, improving processing speed while managing interface complexity.
Data Source
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AI summary
Apparatus and methods for accessing a non-volatile memory (NVM) device in a computer system that includes at least one host processor and at least one memory bus. The NVM device is communicably coupleable to the memory bus through an NVM device controller, thereby allowing the host processor to access persistent data storable within the NVM device by issuing one or more memory load/store commands to the NVM device controller over the memory bus. Because the NVM device controller includes at least one block window or aperture that defines at least one address range for accessing the persistent data storable within the NVM device, the computer system can exploit the full capacity of the NVM device without being unduly constrained by physical addressing limits imposed by the host processor, or by limits imposed by an operating system executed by the host processor.