Non-Volatile Memory Controller Buffering for Parallel Multi-Plane Programming
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Solution Overview
Problem
Non-volatile memory devices face inefficiencies in programming time and increased write amplification factor when dealing with non-sequential logical addresses, as existing multi-plane operations struggle to effectively manage random write requests.
Innovation Solution
A method involving a memory controller that uses a mapping table to store and manage data across multiple planes, allowing for parallel programming of non-sequential data sets by buffering and translating logical addresses into physical addresses for efficient data transmission and storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If multi-plane operation is used for sequential logical addresses, then programming time is shortened, but it cannot be effectively applied to non-sequential logical addresses
Solution Approach 1:
The patent introduces a buffer memory as an intermediary component between the host interface and the non-volatile memory device. This buffer temporarily stores data sets with non-sequential logical addresses, allowing the memory controller to reorder and group them into sequential patterns that enable efficient multi-plane parallel programming operations.
Solution Approach 2:
The patent performs preliminary sorting and grouping of data sets in the buffer memory before programming. By pre-organizing data with non-sequential logical addresses into groups that can be mapped to sequential physical addresses across multiple planes, the system prepares the data in advance to enable parallel programming operations.
2Productivity
If multi-plane operation is used for non-sequential logical addresses, then programming capability is maintained, but write amplification factor increases
Solution Approach 1:
The patent merges multiple data sets with non-sequential logical addresses into a single programming operation by using the buffer memory to collect and group them. This combining approach allows the memory controller to issue fewer, more efficient programming commands to the non-volatile memory device, thereby reducing the total write volume and write amplification factor.
Solution Approach 2:
The patent changes the organizational parameters of data in the buffer memory, transforming data with non-sequential logical address patterns into groups with sequential physical address patterns. This parameter transformation enables the data to be programmed efficiently across multiple planes without increasing write amplification.
3Device complexity
If data with non-sequential logical addresses is programmed directly, then simplicity is maintained, but programming efficiency decreases
Solution Approach 1:
The patent segments the programming process into distinct stages: data reception and buffering, sorting and grouping in the buffer, and parallel programming to the non-volatile memory device. This segmentation allows each stage to be optimized independently, maintaining operational simplicity while dramatically improving overall programming efficiency through multi-plane parallel operations.
Data Source
AI summary
A method of controlling a non-volatile memory device having multiple planes including receiving write requests from a host, the write requests each including a logical address, a write command, and a data set; storing the data sets at an address of a buffer; storing the buffer address in a mapping table that maps addresses of the buffer to the multiple planes; sequentially transmitting the data sets stored at respective buffer addresses to page buffers, respectively, of the planes corresponding to the buffer addresses according to the mapping table; and programming in parallel at least two data sets stored in respective page buffers to memory cells of the non-volatile memory device.