NVM Controller Failure Type Identification in SLC Mode
Solution Overview
Problem
In nonvolatile memory systems programmed in SLC mode using a single programming pulse without verification, there is a challenge in distinguishing between defective memory blocks and under-programmed cells, leading to potential data errors and reduced reliability.
Innovation Solution
A controller is implemented with storage circuitry that communicates with memory devices, disabling program-verification and using a single programming pulse to differentiate between defective and under-programmed memory cells by analyzing bit-flip occurrences, balance measures, threshold-voltage distributions, and error correction codes, enabling corrective actions to prevent under-programming in subsequent operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If program-verification is disabled and a single programming pulse is used, then programming speed is improved, but reliability deteriorates due to inability to distinguish between defective memory blocks and under-programmed cells
Solution Approach 1:
The patent implements a feedback mechanism by reading back the programmed data and analyzing read failures to distinguish between defective memory blocks and under-programmed cells. The system uses bit-flip analysis, threshold-voltage distribution examination, and error pattern recognition to generate feedback that identifies the root cause of programming failures, enabling corrective actions to be taken without requiring traditional program-verification during the programming process itself.
Solution Approach 2:
The patent performs preliminary diagnostic actions by analyzing read failure patterns immediately after programming to determine whether failures are due to defects or under-programming. By conducting this analysis before subsequent operations, the system can proactively adjust programming parameters or mark defective blocks, preventing future data errors without slowing down the initial programming operation.
2Reliability
If traditional program-verification is performed, then reliability is improved, but programming speed deteriorates due to additional read operations
Solution Approach 1:
The patent extracts the verification function from the traditional program-verification process and separates it into a distinct diagnostic analysis phase. Instead of performing verification reads during or immediately after programming, the system extracts the essential verification function by analyzing read failures separately using advanced algorithms that examine bit-flip patterns, threshold-voltage distributions, and error correction code failure modes to distinguish defects from under-programming without requiring multiple verification passes.
Solution Approach 2:
The patent replaces the mechanical verification process (multiple read operations to confirm programming success) with an analytical system that uses error pattern recognition and statistical analysis. Instead of mechanically re-reading data multiple times to verify programming, the system substitutes this with intelligent analysis of single read failure characteristics, using algorithms that can determine programming status from error patterns without requiring repeated physical read operations.
3Measurement precision
If multiple read operations are performed to verify programming, then measurement precision is improved, but loss of time increases
Solution Approach 1:
The patent applies partial verification by performing a single read operation followed by sophisticated analysis of the read results. Instead of requiring multiple complete read operations for verification, the system performs one read and uses advanced algorithms to analyze bit-flip patterns, threshold-voltage distributions, and error patterns to achieve verification accuracy comparable to multiple reads, thereby reducing verification time while maintaining measurement precision.
Data Source
AI summary
A controller includes an interface and storage circuitry. The interface is configured to communicate with a memory device that includes multiple memory cells organized in memory blocks. The memory device supporting programming of the memory cells with enabled or disabled program-verification. The storage circuitry is configured to disable the program-verification, and program data to a group of the memory cells in a Single Level Cell (SLC) mode using a single programming pulse, to read the data from the group of the memory cells. In response to detecting a failure in reading the data, the storage circuitry is configured to distinguish between whether the memory cells in the group belong to a defective memory block or were under-programmed, and when identifying that the memory cells in the group were under-programmed, to perform a corrective action to prevent under-programming in subsequent program operations to the memory cells in the group.